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ST
Sitronix
1. Introduction 2. Features
Single chip TFT-LCD controller/driver with display data RAM Display resolution: 132 (H) x RGB x 132 (V) Display data RAM (frame memory): 132 x 132x 18-bits = 313,632 bits Output: - 396 ch source outputs (132RGB) - 132 ch gate outputs - Common electrode output Display mode (color mode) - Full color mode (idle mode off): 262K-colors - Reduce color mode (idle mode on): 8-colors (1-bit for individual R, G, B color depth) Display resolution - 132 x 132 display with 132 x 18-bits x 132 display RAM Supported LC type option - Transflective (TR) LC type (When LCM1,LCM0 = "00") - Transmissive (TM) LC type (When LCM1,LCM0 = "01") - Low voltage (LV) LC type (When LCM1,LCM0 = "10") - MVA LC type (When LCM1, LCM0 = "11") Supported data format on display host interface - 12-bits/pixel: RGB= (444) using the 384k-bits frame memory and LUT - 16-bits/pixel: RGB= (565) using the 384k-bits frame memory and LUT - 18-bits/pixel: RGB= (666) using the 384k-bits frame memory Supported MCU Interface - 3-line serial interface - 4-line serial interface - 8-bits, 9-bits, 16-bits, 18-bits interface with 8080-series MCU - 8-bits, 9-bits, 16-bits, 18-bits interface with 6800-series MCU - 6-bits, 16-bits, 18-bits RGB interface with graphic controller Display features - Area scrolling - Partial display mode - Software programmable color depth mode Build-in circuit - DC/DC converter - Adjustable VCOM generation - Non-volatile (NV) memory to store initial register setting - Oscillator for display clock generation - Timing controller - Support transflective, transmissive, low voltage, MVA type LC - Factory default value (contrast, module ID, module version, etc) are stored in NV memory - Line inversion, frame inversion NV Memory - 7-bits for ID2 - 8-bits for ID3 - 7-bits for VCOM adjustment
ST7713
262K Color Single-Chip TFT Controller/Driver
The ST7713 is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 396 source line and 132 gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial Peripheral Interface (SPI), 8-bits/9-bits/16-bits/18-bits parallel interface. Display data can be stored in the on-chip display data RAM of 132 x 132 x 18 bits. It can perform display data RAM read/write operation with no external operation clock to minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal, it is possible to make a display system with fewer components.
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. 1
ST7713
Supply voltage range - Analog supply voltage range for VDD to AGND: 2.5V to 3.3V - I/O supply voltage range for VDDI to DGND: 1.6V to 3.3V Output voltage level - Source output voltage range (GVDD to AGND): 3.3V to 5.0V - Power supply range for driver circuit (AVDD to AGND): 4.95V to 6.0V - Output range of HIGH level of VCOM (VCOMH to AGND): 2.5V to 5.0V - Output range of LOW level of VCOM (VCOML to AGND): -2.5V to 0.0V - Output range of HIGH level of gate driver (VGH to AGND): +9.4V to 16.2V - Output range of LOW level of gate driver (VGL to AGND): -13.5V to -7.0V Lower power consumption, suitable for battery operated systems - CMOS compatible inputs - Optimized layout for COG assembly - Operate temperature range: -30 to +70
Ver 1.6
2
2008-05
ST7713
3. Pad arrangement
PADA3 PADB3 DUMMY DUMMY DUMMY PADB2 PADA2 VCOM VCOM VCOM PADB0 VCOML VCOML VCOML VCOMH VCOMH VCOMH VGH VGH_I VGH_I VGL VGL_I VGL_I C23N C23N C23P C23P C22N C22N C22P C22P C21N C21N C21P C21P VCL VCL_I VCL_I AGND AGND AGND C12N C12N C12N C12P C12P C12P C11N C11N C11N C11P C11P C11P GVDD GVDD GVDD AVDD AVDD AVDD_I AVDD_I AVDD_I TPI[2] TPI[1] VREF VREF VREF VDD VDD VDD VDD VDD AGND AGND AGND AGND AGND AGND VCI1 VCI1 VCI1 VCC VCC VCC VDDI VDDI VDDI VDDI VDDI VDDI DGND DGND DGND DGND DGND DGND DGND TPO[1] TPO[2] TPO[3] VS HS DE DGND PCLK DGND D/CX (SCL) DGND RESX SPI-4 GS SDA WRX (R/Wx) RDX (E) CSX TE OSC TPO[4] TPO[5] TPO[6] TPO[7] TPO[8] D0 (SDA) D1 D2 D3 D4 D5 D6 D7 TESEL DGNDO D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 DGNDO LCM1 VDDIO LCM0 TPI[3] TPI[4] DGNDO SHUT VDDIO TB DGNDO RL VDDIO REV DGNDO IDM VDDIO SMY DGNDO SMX VDDIO SRGB DGNDO RCM1 VDDIO RCM0 DGNDO P68 VDDIO IM2 DGNDO IM1 VDDIO IM0 DGNDO EXTC PADA0 PADB1 PADA1
G132 G128
G130
View point: bump view Chip size (um): 13480 x 690 PAD coordinate: pad center Coordinate origin: chip center Chip thickness (um): 30015 Bump height (um): 153 Bump hardness (HV): 7525 Pad arrangement (Unit: um): Output: pad No. 1 ~ 585 = 21 x 96
21 23
96
G4 DUMMY DUMMY DUMMY S396 S394
G2 DUMMY DUMMY DUMMY S395
22
35
96
Input: pad No. 586 ~ 760 = 55 x 96
S3 S1 DUMMY DUMMY DUMMY G3
S2 DUMMY DUMMY DUMMY G1 G5
ST7713 (Bump-up)
Alignment mark (unit: um): (-6627.5, -195.5)
(6627.5, -195.5)
G127 G131
G129
TEST DUMMY PADA4 PADB4
TEST TEST DUMMY DUMMY
Ver 1.6
3
2008-05
ST7713
4. Pad Center Coordinates
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN Name PADA3 DUMMY PADB3 DUMMY DUMMY TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST G132 G130 G128 G126 G124 G122 G120 G118 G116 G114 G112 G110 G108 G106 G104 G102 G100 G98 G96 G94 X 6424 6402 6380 6358 6336 6314 6292 6270 6248 6226 6204 6182 6160 6138 6116 6094 6072 6050 6028 6006 5984 5962 5940 5918 5896 5874 5852 5830 5808 5786 5764 5742 5720 5698 5676 5654 5632 5610 5588 5566 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 PAD No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN Name G92 G90 G88 G86 G84 G82 G80 G78 G76 G74 G72 G70 G68 G66 G64 G62 G60 G58 G56 G54 G52 G50 G48 G46 G44 G42 G40 G38 G36 G34 G32 G30 G28 G26 G24 G22 G20 G18 G16 G14 X 5544 5522 5500 5478 5456 5434 5412 5390 5368 5346 5324 5302 5280 5258 5236 5214 5192 5170 5148 5126 5104 5082 5060 5038 5016 4994 4972 4950 4928 4906 4884 4862 4840 4818 4796 4774 4752 4730 4708 4686 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108
Ver 1.6
4
2008-05
ST7713
PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name G12 G10 G8 G6 G4 G2 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 X 4664 4642 4620 4598 4576 4554 4532 4510 4488 4466 4444 4422 4400 4378 4356 4334 4312 4290 4268 4246 4224 4202 4180 4158 4136 4114 4092 4070 4048 4026 4004 3982 3960 3938 3916 3894 3872 3850 3828 3806 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 PIN Name S368 S367 S366 S365 S364 S363 S362 S361 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 S336 S335 S334 S333 S332 S331 S330 S329 X 3784 3762 3740 3718 3696 3674 3652 3630 3608 3586 3564 3542 3520 3498 3476 3454 3432 3410 3388 3366 3344 3322 3300 3278 3256 3234 3212 3190 3168 3146 3124 3102 3080 3058 3036 3014 2992 2970 2948 2926 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108
Ver 1.6
5
2008-05
ST7713
PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name S328 S327 S326 S325 S324 S323 S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 X 2904 2882 2860 2838 2816 2794 2772 2750 2728 2706 2684 2662 2640 2618 2596 2574 2552 2530 2508 2486 2464 2442 2420 2398 2376 2354 2332 2310 2288 2266 2244 2222 2200 2178 2156 2134 2112 2090 2068 2046 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 PIN Name S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263 S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 X 2024 2002 1980 1958 1936 1914 1892 1870 1848 1826 1804 1782 1760 1738 1716 1694 1672 1650 1628 1606 1584 1562 1540 1518 1496 1474 1452 1430 1408 1386 1364 1342 1320 1298 1276 1254 1232 1210 1188 1166 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108
Ver 1.6
6
2008-05
ST7713
PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 PIN Name S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 X 1144 1122 1100 1078 1056 1034 1012 990 968 946 924 902 880 858 836 814 792 770 748 726 704 682 660 638 616 594 572 550 528 506 484 462 440 418 396 374 352 330 308 286 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 PIN Name S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 DUMMY DUMMY DUMMY DUMMY DUMMY S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 X 264 242 220 198 176 154 132 110 88 66 44 22 0 -22 -44 -66 -88 -110 -132 -154 -176 -198 -220 -242 -264 -286 -308 -330 -352 -374 -396 -418 -440 -462 -484 -506 -528 -550 -572 -594 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108
Ver 1.6
7
2008-05
ST7713
PAD No. 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 PIN Name S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 X -616 -638 -660 -682 -704 -726 -748 -770 -792 -814 -836 -858 -880 -902 -924 -946 -968 -990 -1012 -1034 -1056 -1078 -1100 -1122 -1144 -1166 -1188 -1210 -1232 -1254 -1276 -1298 -1320 -1342 -1364 -1386 -1408 -1430 -1452 -1474 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 PAD No. 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 PIN Name S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 X -1496 -1518 -1540 -1562 -1584 -1606 -1628 -1650 -1672 -1694 -1716 -1738 -1760 -1782 -1804 -1826 -1848 -1870 -1892 -1914 -1936 -1958 -1980 -2002 -2024 -2046 -2068 -2090 -2112 -2134 -2156 -2178 -2200 -2222 -2244 -2266 -2288 -2310 -2332 -2354 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108
Ver 1.6
8
2008-05
ST7713
PAD No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 PIN Name S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 X -2376 -2398 -2420 -2442 -2464 -2486 -2508 -2530 -2552 -2574 -2596 -2618 -2640 -2662 -2684 -2706 -2728 -2750 -2772 -2794 -2816 -2838 -2860 -2882 -2904 -2926 -2948 -2970 -2992 -3014 -3036 -3058 -3080 -3102 -3124 -3146 -3168 -3190 -3212 -3234 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 PAD No. 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 PIN Name S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 X -3256 -3278 -3300 -3322 -3344 -3366 -3388 -3410 -3432 -3454 -3476 -3498 -3520 -3542 -3564 -3586 -3608 -3630 -3652 -3674 -3696 -3718 -3740 -3762 -3784 -3806 -3828 -3850 -3872 -3894 -3916 -3938 -3960 -3982 -4004 -4026 -4048 -4070 -4092 -4114 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108
Ver 1.6
9
2008-05
ST7713
PAD No. 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 PIN Name S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY G1 G3 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 X -4136 -4158 -4180 -4202 -4224 -4246 -4268 -4290 -4312 -4334 -4356 -4378 -4400 -4422 -4444 -4466 -4488 -4510 -4532 -4554 -4576 -4598 -4620 -4642 -4664 -4686 -4708 -4730 -4752 -4774 -4796 -4818 -4840 -4862 -4884 -4906 -4928 -4950 -4972 -4994 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 PAD No. 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 PIN Name G43 G45 G47 G49 G51 G53 G55 G57 G59 G61 G63 G65 G67 G69 G71 G73 G75 G77 G79 G81 G83 G85 G87 G89 G91 G93 G95 G97 G99 G101 G103 G105 G107 G109 G111 G113 G115 G117 G119 G121 X -5016 -5038 -5060 -5082 -5104 -5126 -5148 -5170 -5192 -5214 -5236 -5258 -5280 -5302 -5324 -5346 -5368 -5390 -5412 -5434 -5456 -5478 -5500 -5522 -5544 -5566 -5588 -5610 -5632 -5654 -5676 -5698 -5720 -5742 -5764 -5786 -5808 -5830 -5852 -5874 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108
Ver 1.6
10
2008-05
ST7713
PAD No. 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 PIN Name G123 G125 G127 G129 G131 TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST DUMMY DUMMY PADA4 DUMMY PADB4 PADA1 PADB1 PADA0 EXTC DGNDO IM[0] VDDIO IM[1] DGNDO IM[2] VDDIO P68 DGNDO RCM[0] VDDIO X -5896 -5918 -5940 -5962 -5984 -6006 -6028 -6050 -6072 -6094 -6116 -6138 -6160 -6182 -6204 -6226 -6248 -6270 -6292 -6314 -6336 -6358 -6380 -6402 -6424 -6464 -6400 -6320 -6240 -6160 -6080 -6000 -5920 -5840 -5760 -5680 -5600 -5520 -5440 -5360 Y 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 108 239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 PAD No. 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 PIN Name RCM[1] DGNDO SRGB VDDIO SMX DGNDO SMY VDDIO IDM DGNDO REV VDDIO RL DGNDO TB VDDIO SHUT DGNDO TPI[4] TPI[3] LCM[0] VDDIO LCM[1] DGNDO D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] DGNDO TESEL D[7] D[6] D[5] D[4] X -5280 -5200 -5120 -5040 -4960 -4880 -4800 -4720 -4640 -4560 -4480 -4400 -4320 -4240 -4160 -4080 -4000 -3920 -3840 -3760 -3680 -3600 -3520 -3440 -3360 -3280 -3200 -3120 -3040 -2960 -2880 -2800 -2720 -2640 -2560 -2480 -2400 -2320 -2240 -2160 Y -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239
Ver 1.6
11
2008-05
ST7713
PAD No. 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 PIN Name D[3] D[2] D[1] D[0] (SDA) TPO[8] TPO[7] TPO[6] TPO[5] TPO[4] OSC TE CSX RDX (E) WRX (D/CX) SDA GS 4WSPI RESX DGND D/CX(SCL) DGND PCLK DGND DE HS VS TPO[3] TPO[2] TPO[1] DGND DGND DGND DGND DGND DGND DGND VDDI VDDI VDDI VDDI X -2080 -2000 -1920 -1840 -1760 -1680 -1600 -1520 -1440 -1360 -1280 -1200 -1120 -1040 -960 -880 -800 -720 -640 -560 -480 -400 -320 -240 -160 -80 0 80 160 240 304 368 432 496 560 624 704 768 832 896 Y -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 PAD No. 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 PIN Name VDDI VDDI VCC VCC VCC VCI1 VCI1 VCI1 AGND AGND AGND AGND AGND AGND VDD VDD VDD VDD VDD VREF VREF VREF TPI[1] TPI[2] AVDD AVDD AVDD AVDD_O AVDD_O GVDD GVDD GVDD C11P C11P C11P C11N C11N C11N C12P C12P X 960 1024 1104 1168 1232 1312 1376 1440 1520 1584 1648 1712 1776 1840 1920 1984 2048 2112 2176 2256 2320 2384 2464 2544 2624 2688 2752 2816 2880 2960 3024 3088 3168 3232 3296 3376 3440 3504 3584 3648 Y -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239
Ver 1.6
12
2008-05
ST7713
PAD No. 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 PIN Name C12P C12N C12N C12N AGND AGND AGND VCL VCL VCL_O C21P C21P C21N C21N C22P C22P C22N C22N C23P C23P C23N C23N VGL VGL VGL VGH_O VGH VGH VCOMH VCOMH VCOMH VCOML VCOML VCOML PADB0 VCOM VCOM VCOM PADA2 PADB2 X 3712 3792 3856 3920 4000 4064 4128 4208 4272 4336 4416 4480 4560 4624 4704 4768 4848 4912 4992 5056 5136 5200 5280 5344 5408 5488 5552 5616 5696 5760 5824 5904 5968 6032 6112 6192 6256 6320 6400 6464 Y -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 -239 PAD No. PIN Name X Y
Ver 1.6
13
2008-05
ST7713
5. Block diagram
132 Gate buffer 396 Source buffer Voltage reference
Level shifter DAC Gamma circuit Gate decoder Level Shifter
Data Latch
VCOMH
Gamma Table
Vcom generator
VCOM VCOML
Display Ram 132 x 132 x 18bits
Display control
OSC
C11P
Color conversion LUT table
Instruction register
C11N
OTP Booster 1/2/4
C12P C12N C21P C21N C22P C22N
RGB I/F
MCU IF
C23P C23N
Ver 1.6
14
2008-05
ST7713
6. Pin description 6.1 Power supply pin
Name VDD VDDI AGND DGND I/O I I I I Description Power supply for analog, digital system and booster circuit. Power supply for I/O system. System ground for analog system and booster circuit. System ground for I/O system and digital system. Count 5 6 9 10 Connect pin VDD VDDI GND GND
6.2 Interface logic pin
Description -8080/6800 MCU interface mode select. -P68='1', select 6800 MCU parallel interface. P68 I -P68='0', select 8080 MCU parallel interface. -If not used, please fix this pin at VDDI or DGND level. -Selection for MCU parallel interface or serial interface. IM0~IM2 I -If not used, please fix this pin at VDDI or DGND level. -When in serial interface, this pin can be used to choose 3-line or 4-line 4WSPI I SPI. -If not used, please fix this pin at DGND level. -This signal will reset the device and it must be applied to properly RESX I initialize the chip. -Signal is active low. -Chip selection pin CSX I -Low enable. -Display data/command selection pin in MCU interface. -D/CX='1': display data or parameter. D/CX I -D/CX='0': command data. (SCL) -In serial interface, this is used as SCL. -If not used, please fix this pin at VDDI or DGND level. -Read enable in 8080 MCU parallel interface. RDX I -Read/write operation enable pin in 6800 MCU parallel interface. (E) -If not used, please fix this pin at VDDI or DGND level. -Write enable in MCU parallel interface. WRX -In 4-line serial interface, this pin is used as D/CX (data/ command I (D/CX) selection). -If not used, please fix this pin at VDDI or DGND level. -When RCM1, RCM0='1X' (RGB interface), this pin is used as serial input/output pin. SDA I -When RCM1, RCM0='0X' (MCU interface), this pin is not used and please connect to VDDI or DGND level. The serial input/output pin in MCU interface mode is D0. -Monitoring pin of internal oscillator clock and is turned ON/OFF by S/W command. OSC O -When this pin is inactive (function OFF), this pin is DGND level. -If not used, please open this pin. -When RCM="1" (RGB interface), D[17:0] are used as RGB interface data bus. -When RCM="0" (MCU interface), D[17:0] are used as MCU parallel D[17:0] I/O interface data bus. -D0 is the serial input/output signal in serial interface mode. -In serial interface, D[17:1] are not used and should be connected to VDDI or DGND. -Tearing effect output pin to synchronies MCU to frame rate, activated TE O by S/W command. -If not used, please open this pin. -Pixel clock signal in RGB interface mode. PCLK I -If not used, please fix this pin at VDDI or DGND level. -Vertical sync. signal in RGB interface mode. VS I -If not used, please fix this pin at VDDI or DGND level. -Horizontal sync. signal in RGB interface mode. HS I -If not used, please fix this pin at VDDI or DGND level. -Data enable signal in RGB interface mode. DE I -If not used, please fix this pin at VDDI or DGND level. Note1. When in parallel mode, no use data pin must be connected to "1" or "0". Note2. When CSX="1", there is no influence to the parallel and serial interface. Name I/O Count 1 Connect pin DGND/VDDI
3 1
DGND/VDDI DGND/VDDI
1 1
MCU MCU
1
MCU
1
MCU
1
MCU
1
MCU DGND/VDDI
1
-
18
MCU
1 1 1 1 1
MCU RGB interface RGB interface RGB interface RGB interface
Ver 1.6
15
2008-05
ST7713
6.3 Mode selection pin
Name I/O Description -To use extended command set, please connect this pin to VDDI. -During normal operation, please open this pin (internal Rpull-down=2M ). EXTC Enable/disable modification of extend command 0 Only use default command set 1 Use extended command set -Gamma curve selection pin. GS Selection of gamma curve 0 GC0=1.0, GC1=2.5, GC2=2.2, GC3=1.8 1 GC0=2.2, GC1=1.8, GC2=2.5, GC3=1.0 -Normal mode and idle mode selection pin. IDM Enable/disable idle mode 0 Normal display (can be changed to Idle mode by S/W) 1 Idle mode enable -Liquid crystal (LC) type selection pins. LCM[1:0] Selection of LC type 00 0 TR (transflective) type LC 01 1 TM (transmissive) type LC 10 2 LV (low voltage) type LC 11 3 MVA (multi-domain vertical alignment) type LC -RGB or MCU interface mode selection pins. RCM[1:0] Selection of MCU or RGB interface 00 0 MCU Interface 01 1 MCU Interface 10 2 RGB Interface (1) 11 3 RGB Interface (2) -RGB arrangement selection pin for color filter design. SRGB RGB arrangement S1, S2, S3 filter order = 'R', 'G', 'B' 0 S1, S2, S3 filter order = `B', `G', `R' 1 -Scanning direction of source output selection pin. SMX Scanning direction of source output 0 S1 -> S396 1 S396 -> S1 -Scanning direction of gate output selection pin. SMY Scanning direction of gate output 0 G1 -> G132 1 G132 -> G1 -Polarity of source output selection pin. REV Command Polarity of source output INVON(21h) Data reverse 0 INVOFF(20h) Data not reverse INVON(21h) Data not reverse 1 INVOFF(20h) Data reverse -Display On/Off control pin in RGB2 Interface -Only used in RGB2 mode. If not used, please fix this pin at VDDI or DGND. SHUT Display On/Off 0 Display On 1 Display Off -Scanning direction of source output selection pin in RGB interface. RL SMX Scanning direction of source output 0 0 S1 -> S396 0 1 S396 -> S1 1 0 S396 -> S1 1 1 S1 -> S396 Count Connect pin
EXTC
I
1
VDDI/DGND
GS
I
1
VDDI/DGND
IDM
I
1
VDDI/DGND
LCM1, LCM0
I
2
VDDI/DGND
RCM1, RCM0
I
2
VDDI/DGND
SRGB
I
1
VDDI/DGND
SMX
I
1
VDDI/DGND
SMY
I
1
VDDI/DGND
REV
I
1
VDDI/DGND
SHUT
I
1
VDDI/DGND
RL
I
1
VDDI/DGND
Ver 1.6
16
2008-05
ST7713
TB I -Scanning direction of gate output selection pin in RGB interface. TB SMY Scanning direction of gate output G1 -> G132 0 0 G132 -> G1 0 1 G132 -> G1 1 0 G1 -> G132 1 1 -Input mode: Please fix this pin at VDDI or DGND level. -Output mode: If this pin neither fix on panel internally nor FPC, it must be changed to output mode. (refer to the application note) 1 VDDI/DGND
TESEL
I/O
1
VDDI/DGND
6.4 Driver output pin
Name S1 to S396 G1 to G132 VCI1 AVDD AVDDO VCL VCLO VGH VGHO VGL VREF I/O O O I/O I O I O I O I O - Source driver output pins. - Gate driver output pins. - A reference voltage for step-up circuit 1. - Connect a capacitor for stabilization. - Power input pin for analog circuits. - In normal usage, connect it to AVDDO. - Output of step-up circuit 1 - Connect a capacitor for stabilization. - Power input pin for VCOM circuit. - In normal usage, connect it to VCLO. - A power output pin of step-up circuit 4. - When VCOML is higher than AGND, VCLO=AGND. - Connect a capacitor for stabilization. - Power input pin for gate driver circuit. - In normal usage, connect it to VGHO. - Positive output pin of the step-up circuit 2. - Connect a capacitor for stabilization. - Power input pin for gate driver circuit. - Negative output of the step-up circuit 2 is connected inside the driver. - Connect a capacitor for stabilization. - A reference voltage for power system. - Connect a capacitor for stabilization. - A power output of grayscale voltage generator. - Connect a capacitor for stabilization. - When internal GVDD generator is not used, connect an external power supply (AVDD-0.5V) to this pin. - Positive voltage output of VCOM. - Connect a capacitor for stabilization. - Negative voltage output of VCOM. - Connect a capacitor for stabilization. - A power supply for the TFT-LCD common electrode. Description Count 396 132 3 3 2 2 1 2 1 3 3 Connect pin Capacitor AVDDO Capacitor VCLO Capacitor VGHO Capacitor VGLO Capacitor
GVDD
O
3
Capacitor
VCOMH VCOML VCOM C11P, C11N C12P, C12N C21P, C21N C22P, C22N C23P, C23N VDDIO DGNDO VCC
O O O
3 3 3
Capacitor Capacitor Common electrode Step-up Capacitor
O
- Capacitor connecting pins for step-up circuit 1 (for AVDDO)
12
O
- Capacitor connecting pins for step-up circuit 2 and 4 (for VGHO, VGLO, VCLO)
12
Step-up Capacitor
O O O
-VDDI voltage output level for monitoring. -DGND voltage output level for monitoring. -Monitoring pin of internal digital reference voltage. -Connect a capacitor for stabilization.
8 10 3
Capacitor
Ver 1.6
17
2008-05
ST7713
6.5 Test pin
Name PADA0 PADB0 PADA1 PADB1 PADA2 PADB2 PADA3 PADB3 PADA4 PADB4 TPI[4] TPI[3] TPI[2]~[1] TPO[8]~[1] Dummy I/O I Description -These test pins is for display glass break detection. -If not used, please open these pins. Count 2 Connect pin Open
I
-These test pins is for chip attachment detection. -If not used, please open these pins.
8
Open
I I I O -
-This pin must pull high. -This pin must pull low. -Please open these pins. -Please open these pins. -These pins are dummy (have no function inside). -Can allow signal traces pass through these pads on TFT glass.
1 1 2 8 23
Open Open Open
Ver 1.6
18
2008-05
ST7713
7. Driver electrical characteristics 7.1 Absolute operation range
Item Symbol Rating Unit Supply voltage VDD - 0.3 ~ +4.6 V Supply voltage (Logic) VDDI - 0.3 ~ +4.6 V Supply voltage (Digital) VCC -0.3 ~ +4.6 V Driver supply voltage VGH-VGL -0.3 ~ +30.0 V Logic input voltage range VIN 0.3 ~ VDDI + 0.3 V Logic output voltage range VO 0.3 ~ VDDI + 0.3 V Operating temperature range TOPR -40 ~ +85 Storage temperature range TSTG -55 ~ +125 Note: If one of the above items is exceeded its maximum limitation momentarily, the quality of the product may be degraded. Absolute maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the recommend range.
7.2 DC characteristic
Parameter Power & operation voltage System voltage Interface operation voltage Digital operating voltage Gate driver high voltage Gate driver low voltage Gate driver supply voltage Input / Output Logic-high input voltage Logic-low input voltage Logic-high output voltage Logic-low output voltage Logic-high input current Logic-low input current Input leakage current VCOM voltage VCOM high voltage VCOM low voltage VCOM amplitude Source driver Source output range Gamma reference voltage Source output settling time Output deviation voltage (Source output channel) Symbol VDD VDDI VCC VGH VGL | VGH-VGL | VIH VIL VOH VOL IIH IIL IIL VCOMH VCOML VCOMAC Vsout GVDD Tr Vdev Below with 99% precision Sout >=4.2V, Sout<=0.8V 4.2V>Sout>0.8V Condition Operating voltage I/O supply voltage Digital supply voltage Min 2.5 1.6 1.4 9.41 -13.48 16.47 0.7VDDI VSS 0.8VDDI VSS -1 -0.1 2.5 -2.5 4.0 0.1 3.0 30 20 Specification TYP Max 2.8 1.8/2.8 3.3 3.3 2.0 16.17 -7.06 29.65 VDDI 0.3VDDI VDDI 0.2VDDI 1 +0.1 5.0 0.0 6.0 AVDD-0.1 5.0 Unit V V V V V V V V V V uA uA uA V V V V V us mV mV mV % V % V Note 2 Note 2 Note 3 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Related Pins
IOH = -1.0mA IOL = +1.0mA VIN = VDDI VIN = VSS IOH = -1.0mA Ccom=12nF Ccom=12nF |VCOMH-VCOML|
15 Output offset voltage VOFSET 35 Step-up circuit Internal reference VREF 0 1 voltage 1st step-up (VDDx2) *4 *5 AVDD 4.95 6.0 voltage 1st step-up (VDDx2) drop I AVDD = 1.0mA VDDx2,dorp 5% voltage (with panel loading) Linear range VLinear 0.2 AVDD-0.2 Note 1: VDDI=1.6 to 3.3V, VDD=2.5 to 3.3V, AGND=DGND=0V, TA=-30 to 70 Note 2, Source channel loading= 10pF/channel, Gate channel loading=50pF/channel. Note 3, The Max. value is between measured point of source output and gamma setting value. Note 4, VDD=2.6V or VCI1=2.6V Note 5, VDD=3.0V or VCI1=3.0V
Ver 1.6
19
2008-05
ST7713
7.3 Power consumption
Inversion mode One Line -Normal mode One Line -Partial + Idle mode (40 lines) -Sleep-in mode Notes: 1. All pixels black. 2. Grayscale from top to bottom. 3. Black & white checker board 4 by 4. One Line N/A Note 2 Note 3 N/A 1 1 1 1.1 0.4 0.0004 Current consumption Typical Maximum IDDI IDD IDDI IDD (uA) (mA) (uA) (mA) 1 1.3
Operation mode
Image
Note 1
Ver 1.6
20
2008-05
ST7713
8. Timing chart 8.1 Parallel interface characteristics: 18, 16, 9 or 8-bits bus (8080-series MCU interface)
Fig. 8.1.1 Parallel interface timing characteristics (8080-series MCU interface) Symbol Parameter Min Max TAST Address setup time 5 D/CX TAHT Address hold time (Write/Read) 10 TCHW Chip select "H" pulse width 0 TCS Chip select setup time (Write) 20 TRCS Chip select setup time (Read ID) 20 CSX TRCSFM Chip select setup time (Read FM) 20 TCSF Chip select wait time (Write/Read) 10 TCSH Chip select hold time 20 TWC Write cycle 66 WRX TWRH Control pulse "H" duration 25 Control pulse "L" duration 15 TWRL TRC Read cycle (ID) 160 RDX (ID) TRDH Control pulse "H" duration (ID) 90 TRDL Control pulse "L" duration (ID) 45 TRCFM Read cycle (FM) 169 RDX (FM) TRDHFM Control pulse "H" duration (FM) 90 TRDLFM Control pulse "L" duration (FM) 45 TDST Data setup time 15 TDHT Data hold time 15 D[17:0] TRAT Read access time (ID) 40 TRATFM Read access time (FM) 340 TODH Output disable time 20 80 Note 1: VDDI=1.6 to 3.3V, VDD=2.5 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 Signal Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -
-(3-transfer for one pixel)
When read ID data When read from frame memory
For maximum CL=30pF For minimum CL=8pF
Ver 1.6
21
2008-05
ST7713
Fig. 8.1.2 Rising and falling timing for input and output signal
Fig.8.1.3 Chip selection (CSX) timing
Fig. 8.1.4 Write-to-read and read-to-write timing NOTE: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
Ver 1.6
22
2008-05
ST7713
8.2 Parallel interface characteristics: 18, 16, 9 or 8-bits bus (6800-series MCU interface)
TCHW CSX
VIH VIL
TCHW TCS TRCS/TRCSFM TCSH TCSF
D/CX
VIH VIL
TAST /WX
VIH VIL
TAHT
TWC E
VIL VIH
TWRL TWRH
D[17:0] write
VIH VIL
TDST
TDHT
RX
VIL
VIH
TRDH/TRDHFM E
VIL VIH
TRDL/TRDLFM
TRC/TRCFM TODH
TRAT/TRATFM D[17:0] read
VIH VIL
Fig. 8.2.1 Parallel interface timing characteristics (6800-series MCU interface) Symbol Parameter Min Max Unit Description TAST Address setup time 5 ns D/CX TAHT Address hold time (Write/Read) 10 ns TCHW Chip select "H" pulse width 0 ns TCS Chip select setup time (Write) 20 ns TRCS Chip select setup time (Read ID) 20 ns CSX TRCSFM Chip select setup time (Read FM) 20 ns TCSF Chip select wait time (Write/Read) 5 ns TCSH Chip select hold time 20 ns TWC Write cycle 66 ns WRX TWRH Control pulse "H" duration 25 ns TWRL Control pulse "L" duration 15 ns TRC Read cycle (ID) 160 ns RDX (ID) When read ID data TRDH Control pulse "H" duration (ID) 90 ns TRDL Control pulse "L" duration (ID) 45 ns TRCFM Read cycle (FM) 160 ns When read from frame RDX (FM) TRDHFM Control pulse "H" duration (FM) 90 ns memory TRDLFM Control pulse "L" duration (FM) 45 ns TDST Data setup time 15 ns TDHT Data hold time 15 ns For maximum CL=30pF D[17:0] TRAT Read access time (ID) 40 ns For minimum CL=8pF TRATFM Read access time (FM) 340 ns Output disable time 20 80 ns TODH Note 1: VDDI=1.6 to 3.3V, VDD=2.5 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. Signal
Ver 1.6
23
2008-05
ST7713
8.3 Serial interface characteristics (3-line serial)
Fig. 8.3.1 3-line serial interface timing Signal Symbol TCSS TCSH TCSS TSCC TCHW TSCYCW TSHW TSLW TSCYCR TSHR TSLR TSDS TSDH TACC TOH Parameter Min Max Chip select setup time 45 Chip select hold time 45 Chip select setup time 12 Chip select hold time 20 Chip select "H" pulse width 0 Serial clock cycle (Write) 66 SCL "H" pulse width (Write) 15 SCL "L" pulse width (Write) 15 Serial clock cycle (Read) 150 SCL "H" pulse width (Read) 60 SCL "L" pulse width (Read) 60 Data setup time 10 Data hold time 10 Access time 10 40 Output disable time 40 Table 8.3: 3-line Serial Interface Characteristics Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description
CSX
SCL
SDA (DIN) (DOUT)
For maximum CL=30pF For minimum CL=8pF
Note 1: VDDI=1.6 to 3.3V, VDD=2.5 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
Ver 1.6
24
2008-05
ST7713
8.4 Serial interface characteristics (4-line serial)
VIH VIL
CSX
TCHW TSCYCW/TSCYCR TCSS TCSH
VIH VIL
SCL
TSLW/TSLR TSHW/TSHR TSDS TSDH
TSCC
SDA
VIH VIL
D/CX
VIH VIL
TDCS
TDCH TACC TOH
VIH VIL
SDA (DOUT)
Fig. 8.4.1 4-line serial interface timing Signal Symbol TCSS TCSH TCSS TSCC TCHW TSCYCW TSHW TSLW TSCYCR TSHR TSLR TDCS TDCH TSDS TSDH TACC TOH Parameter MIN MAX Chip select setup time (write) 45 Chip select hold time (write) 45 Chip select setup time (read) 12 Chip select hold time (read) 20 Chip select "H" pulse width 0 Serial clock cycle (Write) 66 SCL "H" pulse width (Write) 15 SCL "L" pulse width (Write) 15 Serial clock cycle (Read) 150 SCL "H" pulse width (Read) 60 SCL "L" pulse width (Read) 60 D/CX setup time 10 D/CX hold time 10 Data setup time 10 Data hold time 10 Access time 10 40 Output disable time 40 Table 8.4: 4-line Serial Interface Characteristics Unit ns ns ns ns ns ns ns ns ns ns ns Ns ns ns ns ns ns Description
CSX
-write command & data ram
SCL
-read command & data ram
D/CX SDA (DIN) (DOUT)
For maximum CL=30pF For minimum CL=8pF
Note 1: VDDI=1.6 to 3.3V, VDD=2.5 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals.
Ver 1.6
25
2008-05
ST7713
9. Function description 9.1 Interface type selection
The selection of given interfaces are done by setting P68, IM2, IM1, and IM0 pins as shown in following table. Table 9.1.1 Selection of MCU interface P68 IM2 IM1 IM0 Interface 0 3-line serial interface 0 1 0 0 8080 MCU 8-bit parallel 0 1 0 1 8080 MCU 16-bit parallel 0 1 1 0 8080 MCU 9-bit parallel 0 1 1 1 8080 MCU 18-bit parallel 0 3-line serial interface 1 1 0 0 6800 MCU 8-bit parallel 1 1 0 1 6800 MCU 16-bit parallel 1 1 1 0 6800 MCU 9-bit parallel 1 1 1 1 6800 MCU 18-bit parallel
Read back selection Via the read instruction RDX strobe (8-bit read data and 8-bit read parameter) RDX strobe (16-bit read data and 8-bit read parameter) RDX strobe (9-bit read data and 8-bit read parameter) RDX strobe (18-bit read data and 8-bit read parameter) Via the read instruction E strobe (8-bit read data and 8-bit read parameter) E strobe (16-bit read data and 8-bit read parameter) E strobe (9-bit read data and 8-bit read parameter) E strobe (18-bit read data and 8-bit read parameter)
Table 9.1.2 Pin connection according to various MCU interface P68 IM2 IM1 IM0 Interface RDX 0 3-line serial interface Note1 0 1 0 0 8080 8-bit parallel RDX 0 0 0 1 1 1 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 8080 16-bit parallel 8080 9-bit parallel 8080 18-bit parallel 3-line serial interface 6800 8-bit parallel 6800 16-bit parallel RDX RDX RDX Note1 E E
WRX Note1 WRX WRX WRX WRX D/CX WRX WRX
D/CX SCL D/CX D/CX D/CX D/CX SCL RS RS RS RS
1 1 1 0 6800 9-bit parallel E WRX 1 1 1 1 6800 18-bit parallel E WRX Note 1. Unused pins can be open, or connected to DGND or VDDI.
Read back selection D[17:1]: unused, D0: SDA D[17:8]: unused, D7-D0: 8-bit data D[17:16]: unused, D15-D0: 16-bit data D[17:9]: unused, D8-D0: 9-bit data D17-D0: 18-bit data D[17:1]: unused, D0: SDA D[17:8]: unused, D7-D0: 8-bit data D[17:16]: unused, D15-D0: 16-bit data D[17:9]: unused, D8-D0: 9-bit data D17-D0: 18-bit data
9.2 8080-series MCU parallel interface (P68='0')
The MCU can use one of following interfaces: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface, 19-line with 16-data parallel interface or 21-lines with 18-data parallel interface. The chip-select CSX (active low) enables/disables the parallel interface. RESX (active low) is an external reset signal. WRX is the parallel data write enable, RDX is the parallel data read enable and D[17:0] is parallel data bus. The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag. When D/CX='1', D[17:0] bits is either display data or command parameter. When D/C='0', D[17:0] bits is command. The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver. The selection of this interface is done when P68 pin is in low state (DGND). Interface bus width can be selected with IM2, IM1 and IM0. The interface functions of 8080-series parallel interface are given in following table. Table 9.2.1 The function of 8080-series parallel interface P68 IM2 IM1 IM0 Interface D/CX RDX WRX Read back selection 0 1 Write 8-bit command (D7 to D0) 8-bit 1 1 Write 8-bit display data or 8-bit parameter (D7 to D0) 0 1 0 0 parallel 1 1 Read 8-bit display data (D7 to D0) 1 Read 8-bit parameter or status (D7 to D0) 1 0 1 Write 8-bit command (D7 to D0) 16-bit 1 1 Write 16-bit display data or 8-bit parameter (D15 to D0) 0 1 0 1 parallel 1 1 Read 16-bit display data (D15 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) 0 1 Write 8-bit command (D7 to D0) 9-bit 1 1 Write 9-bit display data or 8-bit parameter (D8 to D0) 0 1 1 0 parallel 1 1 Read 9-bit display data (D8 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) 0 1 Write 8-bit command (D7 to D0) 18-bit 1 1 Write 18-bit display data or 8-bit parameter (D17 to D0) 0 1 1 1 parallel 1 1 Read 18-bit display data (D17 to D0) 1 Read 8-bit parameter or status (D7 to D0) 1 Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh
Ver 1.6
26
2008-05
ST7713
9.2.1 Write cycle sequence
The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (WRX high-low-high sequence) consists of 3 control signals (D/CX, RDX, WRX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (='0') and vice versa it is data (='1').
Fig. 9.2.1 8080-series WRX protocol Note: WRX is an unsynchronized signal (It can be stopped).
Fig. 9.2.2 8080-series parallel bus protocol, write to register or display RAM
Ver 1.6
27
2008-05
ST7713
9.2.2 Read cycle sequence
The read cycle (RDX high-low-high sequence) means that the host reads information from LCD driver via interface. The driver sends data (D[17:0]) to the host when there is a falling edge of RDX and the host reads data when there is a rising edge of RDX.
Fig. 9.2.3 8080-series RDX protocol Note: RDX is an unsynchronized signal (It can be stopped).
Read parameter
Read display data
D[17:0] RESX "1"
S
CMD
DM
PA
CMD
DM & data
Data
Data
P
CSX
D/CX
RDX
WRX
D[17:0]
S
CMD
DM
PA
CMD
DM & data
Data
Data
P
Host D[17:0] Host to LCD Driver D[17:0] LCD to Host
S
CMD Hi-Z
Hi-Z
CMD Hi-Z
Hi-Z
P
S
DM
PA1
DM & data
PAN-2
PAN-1
P
CMD: write command code PA: parameter or display data
Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored.
Fig. 9.2.4 8080-series parallel bus protocol, read data from register or display RAM
Ver 1.6
28
2008-05
ST7713
9.3 6800-Series Parallel Interface (P68='1')
The MCU uses one of following interface: 11-lines with 8-data parallel interface, 12-lines with 9-data parallel interface, 19-lines with 16-data parallel interface, or 21-lines with 18-data parallel interface. The chip-select CSX(active low) enables and disables the parallel interface. RESX (active low) is an external reset signal. The R/WX is the Read/Write flag and D[17:0] is parallel data bus. The LCD driver reads the data at the falling edge of E signal when R/WX= `1' and Writes the data at the falling of the E signal when R/WX='0'. The D/CX is the data/command flag. When D/CX='1', D[17:0] bits are display RAM data or command parameters. When D/C= `0', D[17:0] bits are commands. The 6800-series bi-directional interface can be used for communication between the micro controller and LCD driver. The selection of this interface is done when P68 pin is high state (VDDI). Interface bus width can be selected with IM2, IM1 and IM0. The interface functions of 6800-series parallel interface are given in Table 9.3.1. Table 9.3.1 The function of 6800-series parallel interface P68 IM2 IM1 IM0 Interface D/CX R/WX E Function 0 0 Write 8-bit command (D7 to D0) 1 0 Write 8-bit display data or 8-bit parameter (D7 to D0) 1 1 0 0 8-bit Parallel 1 1 Read 8-bit Display data (D7 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) 0 0 Write 8-bit command (D7 to D0) 1 0 Write 16-bit display data or 8-bit parameter (D15 to D0) 1 1 0 1 16-bit Parallel 1 1 Read 16-bit Display data (D15 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) 0 0 Write 8-bit command (D7 to D0) 1 0 Write 9-bit display data or 8-bit parameter (D8 to D0) 1 1 1 0 9-bit Parallel 1 1 Read 9-bit Display data (D8 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) 0 0 Write 8-bit command (D7 to D0) 1 0 Write 18-bit display data or 8-bit parameter (D17 to D0) 1 1 1 1 18-bit Parallel 1 1 Read 18-bit Display data (D17 to D0) 1 1 Read 8-bit parameter or status (D7 to D0) Note: applied for command code: DAh, DBh, DCh, 04h, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 0Eh, 0Fh.
9.3.1 Write cycle sequence
The write cycle means that the host writes information (command or/and data) to the display via the interface. Each write cycle (E low-high-low sequence) consists of 3 control signals (D/CX, E, R/WX) and data signals (D[17:0]). D/CX bit is a control signal, which tells if the data is a command or a data. The data signals are the command if the control signal is low (='0') and vice versa it is data (='1').
Fig. 9.3.1 6800-Series Write Protocol
Note: E is an unsynchronized signal (It can be stopped)
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Fig. 9.3.2 6800-series parallel bus protocol, write to register or display RAM
9.3.2 Read cycle sequence
The read cycle (E low-high-low sequence) means that the host reads information from LCD driver via interface. The driver sends data (D[17:0]) to the host when there is a rising edge of E and the host reads data when there is a falling edge of E.
Fig. 9.3.3 6800-series read protocol Note: E is an unsynchronized signal (It can be stopped)
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Read parameter Read display data D[17:0] RESX "1"
S CMD DM PA CMD DM & data Data Data P
CSX
D/CX
R/WX
E
D[17:0]
S
CMD
DM
PA
CMD
DM & data
Data
Data
P
Host D[17:0] Host to LCD Driver D[17:0] LCD to Host
S
CMD Hi-Z
Hi-Z
CMD Hi-Z
Hi-Z
P
S
DM
PA1
DM & data
PAN-2
PAN-1
P
CMD: write command code PA: parameter or display data
Signals on D[17:0], D/CX, R/WX, E pins during CSX=1 are ignored.
Fig. 9.3.4 6800-series parallel bus protocol, read data form register or display RAM
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9.4 Serial interface
The selection of this interface is done by IM2. See the Table 9.4.1. Table 9.4.1 Selection of serial interface IM2 4WSPI Interface 0 0 3-line serial interface 0 1 4-line serial interface
Read back selection Via the read instruction (8-bit, 24-bit and 32-bit read parameter) Via the read instruction (8-bit, 24-bit and 32-bit read parameter)
The serial interface is either 3-lines/9-bits or 4-lines/8-bts bi-directional interface for communication between the micro controller and the LCD driver. The 3-lines serial interface use: CSX (chip enable), SCL (serial clock) and SDA (serial data input/output), and the 4-lines serial interface use: CSX (chip enable), D/CX (data/ command flag), SCL (serial clock) and SDA (serial data input/output). Serial clock (SCL) is used for interface with MCU only, so it can be stopped when no communication is necessary.
9.4.1 Command Write Mode
The write mode of the interface means the micro controller writes commands and data to the LCD driver. 3-lines serial data packet contains a control bit D/CX and a transmission byte. In 4-lines serial interface, data packet contains just transmission byte and control bit D/CX is transferred by the D/CX pin. If D/CX is "low", the transmission byte is interpreted as a command byte. If D/CX is "high", the transmission byte is stored in the display data RAM (memory write command), or command register as parameter. Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX enables the serial interface and indicates the start of data transmission.
Fig. 9.4.1 Serial interface data stream format When CSX is "high", SCL clock is ignored. During the high period of CSX the serial interface is initialized. At the falling edge of CSX, SCL can be high or low (see Fig 9.4.2). SDA is sampled at the rising edge of SCL. D/CX indicates whether the byte is command (D/CX='0') or parameter/RAM data (D/CX='1'). D/CX is sampled when first rising edge of SCL (3-lines serial interface) or 8th rising edge of SCL (4-lines serial interface). If CSX stays low after the last bit of command/data byte, the serial interface expects the D/CX bit (3-lines serial interface) or D7 (4-lines serial interface) of the next byte at the next rising edge of SCL.
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Fig. 9.4.2 3-line serial interface write protocol (write to register with control bit in transmission)
Fig. 9.4.3 4-line serial interface write protocol (write to register with control bit in transmission)
9.4.2 Read Functions
The read mode of the interface means that the micro controller reads register value from the driver. To achieve read function, the micro controller first has to send a command (read ID or register command) and then the following byte is transmitted in the opposite direction. After that CSX is required to go to high before a new command is send (see the below figure). The driver samples the SDA (input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of SCL. Thus the micro controller is supported to read at the rising edge of SCL. After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling edge of SCL of the last bit. 3-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):
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3-line serial protocol (for RDDID command: 24-bit read)
3-line Serial Protocol (for RDDST command: 32-bit read)
Fig. 9.4.4 3-line serial interface read protocol
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4-line serial protocol (for RDID1/RDID2/RDID3/0Ah/0Bh/0Ch/0Dh/0Eh/0Fh command: 8-bit read):
4-line serial protocol (for RDDID command: 24-bit read)
4-line Serial Protocol (for RDDST command: 32-bit read)
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Host Driver
Fig. 9.4.5 4-line serial interface read protocol
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9.5 Data Transfer Break and Recovery
If there is a break in data transmission by RESX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have reset the interface such that it will be ready to receive command data again when the chip select line (CSX) is next activated after RESX have been HIGH state. See the following example
If there is a break in data transmission by CSX pulse, while transferring a command or frame memory data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (CSX) is next activated. See the following example
If 1, 2 or more parameter commands are being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown below.
Host (MCU to driver)
Fig. 9.5.1 Serial bus protocol, write mode - interrupted by RESX
Fig. 9.5.2 Serial bus protocol, write mode - interrupted by CSX
Fig.9.5.3 Write interrupts recovery (serial interface)
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If a 2 or more parameter commands are being sent and a break occurs by the other command before the last one is sent, then the parameters that were successfully sent are stored and the other parameter of that command remains previous value.
Fig. 9.5.4 Write interrupts recovery (both serial and parallel Interface)
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9.6 Data transfer pause
It will be possible when transferring a command, frame memory data or multiple parameter data to invoke a pause in the data transmission. If the chip select line is released after a whole byte of a frame memory data or multiple parameter data has been completed, then driver will wait and continue the frame memory data or parameter data transmission from the point where it was paused. If the chip select Line is released after a whole byte of a command has been completed, then the display module will receive either the command`s parameters (if appropriate) or a new command when the chip select line is next enabled as shown below. This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter
9.6.1 Serial interface pause
Fig. 9.6.1 Serial interface pause protocol (pause by CSX)
9.6.2 Parallel interface pause
Fig. 9.6.2 Parallel bus pause protocol (paused by CSX)
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9.7 Data Transfer Modes
The module has three kinds color modes for transferring data to the display RAM. These are 12-bits color per pixel, 16-bits color per pixel and 18-bits color per pixel. The data format is described for each interface. Data can be downloaded to the frame memory by 2 methods.
9.7.1 Method 1
The Image data is sent to the frame memory in successive frame writes, each time the frame memory is filled, the frame memory pointer is reset to the start point and the next frame is written.
9.7.2 Method 2
Image data is sent and at the end of each frame memory download, a command is sent to stop frame memory write. Then start memory write command is sent, and a new frame is downloaded.
Note: 1) These apply to all data transfer Color modes on both serial and parallel interfaces. 2) The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in the frame memory.
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9.8 Data Color Coding 9.8.1 8-bit Parallel Interface (IM2, IM1, IM0= "100")
Different display data formats are available for three Colors depth supported by listed below. - 4k Colors, RGB 4,4,4-bit input, - 65k Colors, RGB 5,6,5-bit input,. - 262k Colors, RGB 6,6,6-bit input,
9.8.1.1 8-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= "03h"
There are 2 pixels (6 sub-pixels) per 3-bytes.
Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2. 3-time transfer is used to transmit 1 pixel data with the 12-bit color depth information. Note 3. `-` = Don't care - Can be set to '0' or '1'
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9.8.1.2 8-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= "05h"
There is 1 pixel (3 sub-pixels) per 2-bytes.
RESX IM[2:0] CSX D/CX
"1" "100"
WRX RDX R/WX E
6800-series control pins "1" 8080-series control pins "0"
D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 0 1 1 0 0
R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 Pixel n 16 bits
G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0
R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 Pixel n+1 16 bits
G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information. Note 3. `-` = Don't care - Can be set to '0' or '1'
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9.8.1.3 8-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= "06h"
There is 1 pixel (3 sub-pixels) per 3-bytes.
Note1. The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. `-` = Don't care - Can be set to '0' or '1'
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9.8.2 16-Bit Parallel Interface (IM2,IM1, IM0= "101")
Different display data formats are available for three colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input - 65k colors, RGB 5,6,5-bit input - 262k colors, RGB 6,6,6-bit input
9.8.2.1 16-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH= "03h"
There is 1 pixel (3 sub-pixels) per 1 bytes, 12-bit/pixel.
Note1. The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2.1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information.
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9.8.2.2 16-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH= "05h"
There is 1 pixel (3 sub-pixels) per 1 bytes, 16-bit/pixel.
Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information. Note 3. `-` = Don't care - Can be set to '0' or '1'
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9.8.2.3 16-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH= "06h"
There are 2 pixel (6 sub-pixels) per 3 bytes, 18-bit/pixel.
Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. `-` = Don't care - Can be set to '0' or '1'
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9.8.3 9-Bit Parallel Interface (IM2, IM1, IM0="110")
Different display data formats are available for three colors depth supported by listed below. - 262k colors, RGB 6,6,6-bit input
9.8.3.1 Write 9-bit data for RGB 6-6-6-bit input (262k-color)
There are 1 pixel (6 sub-pixels) per 3 bytes, 18-bit/pixel.
RESX IM[2:0] CSX D/CX
"1" "110"
WRX RDX R/WX E
6800-series control pins "1" 8080-series control pins "0"
D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 0 1 1 0 0
R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 Pixel n
G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0
R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 Pixel n+1
G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0
18 bits
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data. Note 2.3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note 3. `-` = Don't care - Can be set to '0' or '1'
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9.8.4 18-Bit Parallel Interface (IM2, IM1, IM0="111")
Different display data formats are available for three colors depth supported by listed below. - 4k colors, RGB 4,4,4-bit input - 65k colors, RGB 5,6,5-bit input - 262k colors, RGB 6,6,6-bit input.
9.8.4.1 18-bit data bus for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH="03h"
There are 1 pixel (3 sub-pixels) per 1 byte, 12-bit/pixel.
RESX IM[2:0] CSX D/CX
"1" "111"
WRX RDX R/WX E
6800-series control pins "1" 8080-series control pins "0"
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 0 1 1 0 0
R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 12 bits
R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 12 bits
R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2
R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
Look-Up Table for 4096 Color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data. Note 2.1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information.
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9.8.4.2 18-bit data bus for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH="05h"
There are 1 pixel (3 sub-pixels) per 1 byte, 16-bit/pixel.
RESX IM[2:0] CSX D/CX
"1" "111"
WRX RDX R/WX E
6800-series control pins "1" 8080-series control pins "0"
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 0 1 1 0 0
R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 16 bits
R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 16 bits
R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2
R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0 for Red and Blue data. Note 2.1-times transfer is used to transmit 1 pixel data with the 16-bit color depth information.
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9.8.4.3 18-bit data bus for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH="06h"
There are 1 pixel (3 sub-pixels) per 1 bytes, 18-bit/pixel.
RESX IM[2:0] CSX D/CX
"1" "111"
WRX RDX R/WX E
6800-series control pins "1" 8080-series control pins "0"
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 0 1 1 0 0
R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n 18 bits
R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 18 bits
R3, Bit 5 R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 5 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2
R4, Bit 5 R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 5 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note1. The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data. Note 2.1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.
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9.8.5 3-line serial Interface
Different display data formats are available for three colors depth supported by the LCM listed below. 4k colors, RGB 4-4-4-bit input 65k colors, RGB 5-6-5-bit input 262k colors, RGB 6-6-6-bit input
9.8.5.1 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH="03h"
Note 1. pixel data with the 12-bit color depth information Note 2. The most significant bits are: Rx3, Gx3 and Bx3 Note 3. The least significant bits are: Rx0, Gx0 and Bx0
9.8.5.2 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH="05h"
Note 1. pixel data with the 16-bit color depth information Note 2. The most significant bits are: Rx4, Gx5 and Bx4 Note 3. The least significant bits are: Rx0, Gx0 and Bx0
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9.8.5.3 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH="06h"
Note 1. pixel data with the 18-bit color depth information Note 2. The most significant bits are: Rx5, Gx5 and Bx5 Note 3. The least significant bits are: Rx0, Gx0 and Bx0
9.8.6 4-line serial Interface
Different display data formats are available for three colors depth supported by the LCM listed below. 4k colors, RGB 4-4-4-bit input 65k colors, RGB 5-6-5-bit input 262k colors, RGB 6-6-6-bit input
9.8.6.1 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3AH="03h"
Note 1. pixel data with the 12-bit color depth information Note 2. The most significant bits are: Rx3, Gx3 and Bx3 Note 3. The least significant bits are: Rx0, Gx0 and Bx0
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9.8.6.2 Write data for 16-bit/pixel (RGB 5-6-5-bit input), 65K-Colors, 3AH="05h"
Note 1. pixel data with the 16-bit color depth information Note 2. The most significant bits are: Rx4, Gx5 and Bx4 Note 3. The least significant bits are: Rx0, Gx0 and Bx0
9.8.6.3 Write data for 18-bit/pixel (RGB 6-6-6-bit input), 262K-Colors, 3AH="06h"
Note 1. pixel data with the 18-bit color depth information Note 2. The most significant bits are: Rx5, Gx5 and Bx5 Note 3. The least significant bits are: Rx0, Gx0 and Bx0
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9.9 RGB interface 9.9.1 General Description
The module uses 6, 16 and 18-bit parallel RGB interface which includes: VS, HS, DE, PCLK, D[17:0]. The interface is activated after Power-On sequence (See section Power-On/Off Sequence) Pixel clock (PCLK) is running all the time without stopping and it is used to enter VS, HS, DE and D[17:0] states at the rising edge of the PCLK. The PCLK cannot be used as continues internal clock for other functions of the display module e.g. Sleep-In mode etc. Vertical synchronization (VS) is used to tell the driver when a new frame of the display is beginning. This is negative (`0', low) active and its state is read by the driver at the rising edge of he PCLK signal. Horizontal synchronization (HS) is used to tell the driver when a new line of the frame is beginning. This is negative (`0', low) active and its state is read by the driver at the rising edge of the PCLK signal. Data Enable (DE) is used to tell the driver when the RGB information will be transferred ti the driver. This is a positive (`1', high) active and its state is read by the driver at the rising edge of the PCLK signal. D[17:0] (18-bit: R5-R0, G5-G0 and B5-B0; 16-bit: R4-R0, G5-G0 and B4-B0) are used to tell what is the information of the image that is transferred on the display (When DE='1' and at the rising edge of PCLK). D[17:0] can be `0' (low) or `1' (high). These lines are read by the driver at the rising edge of the PCLK signal. The PCLK cycle is described in the following figure.
Fig. 9.9.1 PCLK cycle Note: PCLK is an unsynchronized signal (It can be stopped).
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9.9.2 General timing diagram
Fig. 9.9.2 RGB general timing diagram The image information must be correct on the display, when the timings conforms the spec of the RGB interface. However, the image information can be incorrect on the display temporarily when timing is out of spec. The correct image information must be displayed automatically (by the display module) in the next frame period as the timing recovers from out of spec to within spec.
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9.9.3 Updating order on display active area (normal display mode On + sleep out)
There are different kinds of updating orders for the display. These updating orders are controlled by H/W (SMX, SMY) and S/W (MX, MY, MV) bits.
Fig. 9.9.3 Updating order when MADCTL's MX="0" and MY="0"
Fig. 9.9.4 Updating order when MADCTL's MX="1" and MY="0"
Fig. 9.9.5 Updating order when MADCTL's MX="0" and MY="1"
Vertical active counter (0 ~ 131)
Fig. 9.9.6 Updating order when MADCTL's MX="1" and MY="1"
Vertical active counter (0 ~ 131)
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Table 9.9.1 Rules for updating order Condition Horizontal Counter Return to 0 Increment by 1 Return to 0 Return to 0 Vertical Counter Return to 0 No change Increment by 1 Return to 0 An active VS signal is received Signal pixel information of the active area is received An active HS signal between two active area lines The horizontal counter is larger than 239 and the vertical counter is larger than 319 Note 1. Pixel order is RGB on the display. Note 2. Data streaming direction from the host to the display is described in the following figure.
Fig. 9.9.3 Data streaming order for RGB interface
9.9.4 RGB Interface Bus Width set
All 4-kinds of bus width can be available in RGB interface mode (selected by COLMOD (3Ah) command for 6-bit, 16-bit and 18-bit data width) VIPF[3:0] 0101 0110 D17 R4 R5 D16 R3 R4 D15 R2 R3 D14 R1 R2 D13 R0 R1 D12 x R0 D11 G5 G5 D10 G4 G4 D9 G3 G3 D8 G2 G2 D7 G1 G1 D6 G0 G0 D5 B4 B5 D4 B3 B4 D3 B2 B3 D2 B1 B2 D1 B0 B1 D0 x B0 Bus width 16-bit data 18-bit data 6-bit data
x x x x x x x x x x X x R5 R4 R3 x x x x x x x x x x X X G5 G4 G3 x x x x x x x x x x x X B5 B4 B3 Note 1: When VIPF[3:0]="1110", 6-bit data width of 3-times transfer is used to transmit 1 pixel data with depth information. Note 2: Only VIPF[3:0]= "0101" , "0110" and "1110" are valid on RGB I/F, Others are invalid. Note 3. `x' Don't care, but need to set VDDI or DGND level. 1110
R2 R1 R0 G2 G1 G0 B2 B1 B0 the 18-bit color
9.9.5 RGB Interface Mode Set
Table 9.9.5.1 RGB Interface Mode Setting RGB I/F PCLK DE VS Mode RGB Mode 1 Used Used Used RGB Mode 2 Used Used Used HS Used Used Video Data bus D[17:0] Used Used Register for Blanking Porch setting Not Used Used Reference clock for Display Internal Oscillator Internal Oscillator
There are 2-kinds of RGB mode which is selected by RCM1 & RCM0 hardware pins. In RGB Mode 1 (RCM1, RCM0 = "10"), writing data to frame memory is done by PCLK and data bus (D[17:0]), when DE is in high state. The external synchronization signals (PCLK, VS and HS) are used for internal display signals. So, controller (host) must always transfer PCLK, VS, HS and DE signals to driver. In RGB Mode 2 (RCM1, RCM0 = "11"), blanking porch setting of VS and HS signals are defined by RGBBPCTR (B5h) command. DE pin is used for data making. When DE pin is high, valid data is directly stored to frame memory. In the contrast, if DE pin is low the data of frame memory will keep same status.
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9.9.6 RGB Interface Timing Diagram 9.9.6.1 General Timings for RGB I/F
Fig. 9.9.6 General timing of RGB interface Table 9.9.6.1 General Timing for RGB I/F Specification Min Type. Max Pixel low pulse width TPCLKLT 15 Pixel high pulse width TPCLKHT 15 Vertical Sync. set-up time TVSST 15 Vertical Sync. hold time TVSSHT 15 Horizontal Sync. set-up time THSST 15 Horizontal Sync. hold time TVSSHT 15 Data Enable set-up time TDEST 15 Data Enable hold time TDEHT 15 Data set-up time TDST 15 Data hold time TDHT 15 Note 1: VDDI=1.6 to 3.3V, VDD=2.5 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 (to +85 no damage) Note 2: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. Note 3. Data lines can be set to "High" or "Low" during blanking time - Don't care. Note 4. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. Note 5. HP is multiples of eight PCLK. Item Symbol Condition Unit
ns ns ns ns
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VS n frame n+1 frame n+2 frame
HS
PCLK
DE *
DE ** don't care Data
Frame data frame data DE * = RGB mode 1 DE ** = RGB mode 2 frame data RAM write command (2Ch) address set command (2Ah, 2Bh) data transfer (ICM="1") data transfer (ICM="1")
Fig. 9.9.7 RAM access via SPI interface in RGB mode Note: DP='0', EP='0', HSP='0' and VSP='0' of RGBCTR (B0h) command.
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9.9.6.2 RGB Interface Mode 1 Timing Diagram
Fig. 9.9.8 RGB mode 1 timing diagram Note: DP='0', EP='0', HSP='0' and VSP='0' of RGBCTR (B0h) command.
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Fig. 9.9.9 Vertical and horizontal timing of RGB interface Table 9.9.6.2 Vertical and Horizontal Timing for RGB I/F Item Vertical Timing Vertical cycle period Vertical low pulse width Vertical front porch Vertical back porch Vertical data start line Vertical blanking period Vertical active area Vertical refresh rate Horizontal Timing Horizontal cycle period Horizontal low pulse width Horizontal front porch Horizontal back porch Horizontal data start point Horizontal blanking period Horizontal active area Symbol TVP TVS TVFP TVBP TVBL TVDISP TVRR THP THS THFP THBP TVS + TVBP TVS + TVBP + TVFP Frame rate Condition Min 134 2 2 2 4 6 61.75 152 2 2 2 30 32 130 65 Specification Type. Max 140 4 4 4 8 12 68.25 745 256 256 256 766 768 120 718 10 Unit HS HS HS HS HS HS HS Hz PCLK PCLK PCLK PCLK PCLK PCLK PCLK ns MHz
THS + THBP THBL THDISP TPCLKCYC 100 Pixel clock cycle fPCLKCYC 1.4 Note 1. VDDI=1.6 to 3.3V, VDD=2.5 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 Note 2. HP is multiples of eight PCLK.
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9.9.6.3 RGB Interface Mode 2 Timing Diagram
V back porch (TVS+TVBP) VS
1 frame (TVP) V front porch (TVFP)
HS
DE "1"
HS H back porch (THS+THBP) PCLK
1 line (THP) Valid data (THDISP) H front porch (THFP)
DE "1"
Data bus
Invalid
D1 D2 D3
Dn
Invalid
Latch data
Invalid
D1 D2 D3
Dn
Fig. 9.9.10 RGB mode 2 timing diagram
Fig. 9.9.11 RGB mode 2 vertical timing diagram Note: DP='0', EP='0', HSP='0' and VSP='0' of RGBCTR (B0h) command.
Horizontal timing for RGB I/F
HS THS+THBP=10 PCLK D[17:0] Invalid THP= 150 PCLK PCLK THDISP=130 PCLK
THFP=10 PCLK Invalid
Fig. 9.9.12 RGB mode 2
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Fig. 9.9.13 RGB mode 2 idle mode timing diadram Note: DP='0', EP='0', HSP='0' and VSP='0' of RGBCTR (B0h) command.
Fig. 9.9.14 Vertical and Horizontal in RGB interface
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Table 9.9.6.3 Vertical and Horizontal Timing for RGB I/F Item Vertical Timing Vertical cycle period Vertical low pulse width Vertical front porch Vertical back porch Vertical data start line Vertical blanking period Vertical active area Vertical refresh rate Horizontal Timing Horizontal cycle period Horizontal low pulse width Horizontal front porch Horizontal back porch Horizontal data start point Horizontal blanking period Horizontal active area Symbol TVP TVS TVFP TVBP TVBL TVDISP TVRR THP THS THFP THBP TVS + TVBP TVS + TVBP + TVFP Frame rate Condition Min 131 1 1 1 2 3 61.75 131 1 1 1 1 3 Specification Type. Max 132 1 3 4 130 65 4 1023 1023 1023 1023 68.25 511 63 63 63 63 256 896 10 Unit HS HS HS HS HS HS HS Hz PCLK PCLK PCLK PCLK PCLK PCLK PCLK ns MHz
THS + THBP THBL THDISP TPCLKCYC 100 Pixel clock cycle fPCLKCYC 1.12 Note 1. VDDI=1.6 to 3.3V, VDD=2.5 to 3.3V, AGND=DGND=0V, Ta=-30 to 70 Note 2. Data lines can be set to "High" or "Low" during blanking time - Don't care. Note 3. HP is multiples of eight PCLK.
10 20 130 788 1.27
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9.9.6.4 Power On Sequence on RGB Mode 2
The Driver operates power up and display ON by VDD, VDDI, SHUT, VS, HS, DE, PCLK on RGB mode 2 as show as following figure.
VDD
TVDD-VDDI
VDDI RESX SHUT PCLK HS DE 1 VS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TRS-SH
TVDD-SH TPCLK-SH
Display high voltage Display Source output Vcom output Gate output Internal counter Internal oscillator
TSH-LCD TSH-ON Blanking display (over 1 frame)
Display on Normal display Normal display Normal display
Fig. 9.9.15 Power-ON sequence in RGB mode 2 Table 9.9.6.4 Power ON AC Characteristics Characteristics Symbol Min Typ Max Unit VDD On to VDDI On TVDD-VDDI 0 ns VDDI/VDD on to falling edge of SHUT TVDD-SH 1 ms RESX to falling of SHUT TRS-SH 10 us Signals input to falling edge of SHUT * TCLK-SH 1 PCLK Falling edge of SHUT to LCD power ON TSH-LCD 120 ms Falling edge of SHUT to Display start TSH-ON 10 VS Note 1: TVDDI-VDD can be <=0ns, >0ns. In any case, VDDI and VDD power up sequence should not have any the driver / display functionalities / performance. Note 2: Signals mean VS, HS, DE and PCLK signal. Note 3: DP='0', EP='0', HSP='0' and VSP='0' of RGBCTR (B0h) command.
Remark Note1
Note2
impact on
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9.9.6.5 Power OFF Sequence on RGB Mode 2
The Driver operates power off and display OFF by VDD, VDDI, SHUT, VS, HS and DE on RGB mode 2 as show as following figure.
VDDI TVDD-VDDI VDD
RESX
SHUT TOFF-VDD PCLK TSH-OFF
HS
DE
VS
Display high voltage Display
Display on
Display off
Normal display
Source output
Normal display
0V
Blanking display (over 1 frame)
Vcom output
Normal display
0V
Gate output
Internal counter Internal oscillator
Fig. 9.9.16 Power-OFF seqnence in RGB mode 2 Table 9.9.6.5 Power OFF AC Characteristics Characteristics Symbol Min Typ Max Unit Remark VDDI On to VDD On TVDDI-VDD 0 ns Note1 Signals input to VDDI/VDD off TSH-OFF 1 us Note2 Rising edge of SHUT to Display off TSH-OFF 2 VS Note 1: TVDDI-VDD can be <=0ns, >0ns. In any case, VDDI and VDD power up sequence should not have any impact on the driver / display functionalities / performance. Note 2: Signals mean VS, HS, DE and PCLK signal. Note 3: DP='0', EP='0', HSP='0' and VSP='0' of RGBCTR (B0h) command.
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9.9.7 RGB Data Color Coding 9.9.7.1 16-bit/pixel Color Order on the RGB Interface
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Green data and MSB=Bit4, LSB=Bit0 for Red and Blue data. Note 2. `-' Don't care, but need set to VDDI or DGND level.
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9.9.7.2 18-bit/pixel Color Order on the RGB Interface
"1" "10"or "11" "1" "1" "1"
RESX RCM[1:0] VS HS DE PCLK
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R1, Bit 5 R1, Bit 4 R1, Bit 3 R1, Bit 2 R1, Bit 1 R1, Bit 0 G1, Bit 5 G1, Bit 4 G1, Bit 3 G1, Bit 2 G1, Bit 1 G1, Bit 0 B1, Bit 5 B1, Bit 4 B1, Bit 3 B1, Bit 2 B1, Bit 1 B1, Bit 0 Pixel n
R2, Bit 5 R2, Bit 4 R2, Bit 3 R2, Bit 2 R2, Bit 1 R2, Bit 0 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel n+1 18 bits
R3, Bit 5 R3, Bit 4 R3, Bit 3 R3, Bit 2 R3, Bit 1 R3, Bit 0 G3, Bit 5 G3, Bit 4 G3, Bit 3 G3, Bit 2 G3, Bit 1 G3, Bit 0 B3, Bit 5 B3, Bit 4 B3, Bit 3 B3, Bit 2 B3, Bit 1 B3, Bit 0 Pixel n+2 18 bits
R4, Bit 5 R4, Bit 4 R4, Bit 3 R4, Bit 2 R4, Bit 1 R4, Bit 0 G4, Bit 5 G4, Bit 4 G4, Bit 3 G4, Bit 2 G4, Bit 1 G4, Bit 0 B4, Bit 5 B4, Bit 4 B4, Bit 3 B4, Bit 2 B4, Bit 1 B4, Bit 0 Pixel n+3
R5, Bit 5 R5, Bit 4 R5, Bit 3 R5, Bit 2 R5, Bit 1 R5, Bit 0 G5, Bit 5 G5, Bit 4 G5, Bit 3 G5, Bit 2 G5, Bit 1 G5, Bit 0 B5, Bit 5 B5, Bit 4 B5, Bit 3 B5, Bit 2 B5, Bit 1 B5, Bit 0 Pixel n+4
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data. Note 2. `-' Don't care, but need set to VDDI or DGND level.
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9.9.7.3 6-bit/pixel Color Order on the RGB Interface
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit5, LSB=Bit0 for Red, Green and Blue data. Note 2. `-' Don't care, but need set to VDDI or DGND level.
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9.10 Display Data RAM 9.10.1 Configuration
The display module has an integrated 132x132x18-bit graphic type static RAM. This 384,912-bit memory allows to store on-chip a 132RGBx132image with an 18-bpp resolution (262K-color). There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Read or Write to the same location of the Frame Memory.
Fig. 9.10.1 Display data RAM organization
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9.10.2 Memory to Display Address Mapping 9.10.2.1 When using 132RGB x 132 resolution (SMX=SMY=SRGB='0')
Pixel 1 Pixel 2 -------Pixel 131 Pixel 132
Gate Out
Source Out
S1 RGB=0
S2
S3 RGB=1
S4 RGB=0
S5
S6 -------- S391 S392 S393 S394 S395 S396 RGB=1 RGB=0 RGB=1 RGB=0 SA ML=' 0 ' ML=' 1 ' B1 -------- R130 G130 B130 R131 G131 B131 0 131 -------1 130 -------2 129 -------3 128 -------4 127 -------5 126 -------6 125 -------7 124 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -------124 7 -------125 6 -------126 5 -------127 4 -------128 3 -------129 2 -------130 1 -------131 0 128 129 -------1 0 -------RGB Order RGB=1
2 3 4 5 6 7 8 9 | | | | | 124 125 126 127 128 129 130 131
RA MY=' 0 ' MY=' 1 ' 0 131 R0 1 130 2 129 3 128 4 127 5 126 6 125 7 124 | | | | | | | | | | | | | | | 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 MX=' 0 ' CA MX=' 1 '
G0
B0
R1
G1
| | | | |
| | | | |
| | | | |
| | | | |
0 129
1 128
Note RA = Row Address, CA = Column Address SA = Scan Address MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command MX =Scan direction parameter, D4 parameter of MADCTL command RGB = Red, Green and Blue pixel position change, D3 parameter of MADCTL command
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9.10.3 Normal Display On or Partial Mode On, Vertical Scroll Off
9.10.3.1 When using 132RGB x 132 resolution In this mode, contents of the frame memory within an area where column pointer is 00h to 83h and page pointer is 000h to 083h is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (0, 0). 1). Example for Normal Display On (MX=MY=ML='0', SMX=SMY='0')
132 Columns Scan Order
00h 00h 00 01h 10 02h 20 | 30 | 40 | | | W0 7Fh X0 80h Y0 81h Z0 01h ---- ---- ---- ---- 80h 01 02 0X 0Y 11 12 1X 1Y 21 31 130 x 130 x 18 bit Fram e RAM W1 X1 Y1 Y2 Z1 Z2 WZ XZ YX YY YZ ZX ZY ZZ "Unused area" 128 129 130 81h 83h 0Z 1Z 2Z
132 Columns
1 2 3 | |
00h 00 10 20 30 40
W0 X0 Y0 Z0
01h ---- ---- ---- ---- ---- 82h 83h 01 02 0X 0Y 0Z G2 11 12 1X 1Y 1Z G3 21 2Z G4 31 3Z | 4Z | | 132RGB x 132 LCD Panel | W1 WZ | X1 XZ G130 Y1 Y2 YX YY YZ G131 Z1 Z2 ZX ZY ZZ G132
Display area =132 lines
2). Example for Partial Display On (PSL[7:0]=03h,PEL[7:0]=7Eh, MX=MV=ML='0' ,SMX=SMY='0')
Scan Order
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132 Lines 132 Lines
A1h
132 Columns
132 Columns
00h 01h 02h | | | | | 81h 82h 83h
00h 00 10 20 30 40
01h ---- ---- ---- ---- 7Eh 01 02 0X 0Y 11 12 1X 1Y 21 31 132 x 132 x 18 bit Frame RAM
7Fh 83h 0Z 1Z 2Z 3Z 4Z
W0 X0 Y0 Z0
W1 X1 Y1 Y2 Z1 Z2
WZ XZ YX YY YZ ZX ZY ZZ "Unused area"
1 2 3 | | | | | 130 131 132
00 10 20 30 40
01 02 11 12 21 31
A1h
W0 X0 Y0 Z0
W1 X1 Y1 Z1
0X 0Y 0Z G2 1X 1Y 1Z G3 2Z G4 3Z | 4Z | | 132RGB x 132 LCD Panel | WZ | XZ G130 Y2 YX YY YZ G131 Z2 ZX ZY ZZ G132
Non-Display area =3 lines
Display area =126 lines
Non-Display area =3 lines
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9.10.4 Vertical Scroll Mode There is vertical scrolling, which are determined by the commands "Vertical Scrolling Definition" (33h) and Vertical Scrolling Start Address" (37h).
Fig. 9.10.2 Difference between Scrolling and original
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9.10.4.1 When using 132RGB x 132 resolution When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=132. In this case, scrolling is applied as shown below. 1). Example for TFA =2, VSA=123, BFA=2, SSA=3, ML=0: Scrolling
128 Columns Scan Order 128 Columns
00h 01h 02h | | | | | 7Fh 80h 81h
00h 00 10 20 30 40
01h ---- ---- ---- ---- 7Eh 7Fh 83h 01 02 0X 0Y 0Z 11 12 1X 1Y 1Z 21 2Z 31 130 x 130 x 18 bit Fram e RAM
TFA
1 2 3 | |
SSA
00 10 30 40
01 11 31
02 12
0X 0Y 0Z 1X 1Y 1Z 3Z 4Z 130RGB x 130 LCD Panel
W0 X0 Y0 Z0
W1 X1 Y1 Y2 Z1 Z2
WZ XZ YX YY YZ ZX ZY ZZ "Unused area"
128 129 130
X0 20 Y0 Z0
X1 21 Y1 Y2 Z1 Z2
XZ 2Z YX YY YZ ZX ZY ZZ
G2 G3 G4 | | | | | G129 G130 G131
2). Example for TFA =2, VSA=123, BFA=2, SSA=3, ML=1: Scrolling: TFA and BFT are exchanged
128 Columns Scan Order 128 Columns
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128 Lines 128 Lines
VSA
BFA
A1h
00h 01h 02h | | | | | 7Fh 80h 81h
00h 00 10 20 30 40
W0 X0 Y0 Z0
01h ---- ---- ---- ---- 7Eh 7Fh 83h 01 02 0X 0Y 0Z 130 11 12 1X 1Y 1Z 129 21 2Z 128 31 | | 130 x 130 x 18 bit Fram e RAM SSA W1 WZ X1 XZ 3 Y1 Y2 YX YY YZ 2 Z1 Z2 ZX ZY ZZ 1 "Unused area"
00 01 02 10 11 12 X0 X1 20 130RGB x 130 LCD Panel V0 W0 Y0 Z0 V1 W1 Y1 Y2 Z1 Z2
0X 0Y 0Z 1X 1Y 1Z XZ 2Z
VZ WZ YX YY YZ ZX ZY ZZ
G2 G3 G4 | | | | | G129 G130 G131
BFA
VSA
TFA
A1h
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9.10.5 Vertical Scroll Example 9.10.5.1 Vertical Scroll Example There are 2 types of vertical scrolling, which are determined by the commands " Vertical Scrolling Definition" (33h) and "Vertical Scrolling Start Address" (37h). Case 1: TFA + VSA + BFA132 N/A. Do not set TFA + VSA + BFA132. In that case, unexpected picture will be shown. Case 2: TFA + VSA + BFA=132 (Scrolling) Example1) When MADCTL parameter ML="0", TFA=0, VSA=132, BFA=0 and VSCSAD=40.
Example2) When MADCTL parameter ML="1", TFA=30, VSA=98, BFA=0 and VSCSAD=40.
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9.11 Address Counter
The address counter sets the addresses of the display data RAM for writing and reading. Data is written pixel-wise into the RAM matrix of DRIVER. The data for one pixel or two pixels is collected (RGB 6-6-6-bit), according to the data formats. As soon as this pixel-data information is complete the "Write access" is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=131 (83h) and Y=0 to Y=131 (83h). Addresses outside these ranges are not allowed. Before writing to the RAM, a window must be defined that will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=131 (83h), YE=131 (83h). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands "CASET, RASET" and "MADCTL" (see section 10 command list), define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Section 9.12 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM. For each image condition, the controls for the column and row counters apply as section 9.12 below: Condition Column Counter Return to "Start When RAMWR/RAMRD command is accepted Column (XS)" Complete Pixel Read / Write action Increment by 1 Return to "Start The Column counter value is larger than "End Column (XE)" Column (XS)" The Column counter value is larger than "End Column (XE)" and Return to "Start the Row counter value is larger than "End Row (YE)" Column (XS)"
Row Counter Return to "Start Row (YS)" No change Increment by 1 Return to "Start Row (YS)"
9.12. Memory Data Write/ Read Direction
The data is written in the order illustrated above. The Counter which dictates where in the physical memory the data is to be written is controlled by "Memory Data Access Control" Command, bits B5 (MV), B6 (MX), B7 (MY) as described below.
Fig. 9.12.1 Data streaming order
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9.12.1.1 When 132RGBx132
MV
Virtual physical point translator
CASET (2Ah)
CASET (2Bh)
MADCTL (36h)
MX MY
Virtual (0, 0) When MV=don't care, MX="0", MY="0" (0, 0) Physical row point
Physical column point
Virtual (0, 0) When MV=don't care, MX="1", MY="0"
(131, 0)
Physical SRAM
(0, 131) Virtual (0, 0) When MV=don't care, MX="0", MY="1"
(131, 131) Virtual (0, 0) When MV=don't care, MX="1", MY="1"
MV 0 0 0 0 1 1 1 1
MX 0 0 1 1 0 0 1 1
MV 0 1 0 1 0 1 0 1
CASET Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (131-Physical Column Pointer) Direct to (131-Physical Column Pointer) Direct to Physical Row Pointer Direct to (131-Physical Row Pointer) Direct to Physical Row Pointer Direct to (131-Physical Row Pointer)
RASET Direct to Physical Row Pointer Direct to (131-Physical Row Pointer) Direct to Physical Row Pointer Direct to (131-Physical Row Pointer) Direct to Physical Column Pointer Direct to Physical Column Pointer Direct to (131-Physical Column Pointer) Direct to (131-Physical Column Pointer)
Note: Data is always written to the Frame Memory in the same order, regardless of the Memory Write Direction set by MADCTL bits B7 (MY), B6 (MX), B5 (MV). The write order for each pixel unit is
One pixel unit represents 1 column and 1page counter value on the Frame Memory.
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9.12.2 Frame Data Write Direction According to the MADCTL parameters (MV, MX and MY)
Display Data Direction Normal MADCTL Parameter MV MX MY 0 0 0 Image in the Host (MPU) Image in the Driver (DDRAM)
H/W position (0,0) X-Y address (0,0) X: CASET Y: RASET H/W position (0,0) X-Y address (0,0) X: CASET Y: RASET H/W position (0,0)
B
B
F
Y-Mirror 0 0 1
F F
B
F
X-Mirror 0 1 0
B B
X-Y address (0,0) X: CASET Y: RASET
B
F
X-Mirror Y-Mirror 0 1 1
F
H/W position (0,0)
B
F
X-Y address (0,0) X: CASET
F
X-Y Exchange 1 0 0
B
H/W position (0,0) X-Y address (0,0) X: RASET Y: CASET H/W position (0,0) X-Y address (0,0) X: RASET Y: CASET H/W position (0,0)
Y: RASET
B
B
F
X-Y Exchange Y-Mirror 1 0 1
B
F F
F
X-Y Exchange X-Mirror 1 1 0
B B
X-Y address (0,0) X: RASET Y: CASET
B
F
X-Y Exchange X-Mirror Y-Mirror 1 1 1
B
H/W position (0,0)
F B
X-Y address (0,0) X: RASET
F
F
Y: CASET
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9.13 Tearing Effect Output Line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On command. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images.
9.13.1 Tearing Effect Line Modes
Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:
tvdh= The LCD display is not updated from the Frame Memory tvdl= The LCD display is updated from the Frame Memory (except Invisible Line - see below) Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one V-sync and 132 H-sync pulses per field.
thdh= The LCD display is not updated from the Frame Memory thdl= The LCD display is updated from the Frame Memory (except Invisible Line - see above)
Note: During Sleep In Mode, the Tearing Output Pin is active Low.
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9.13.2 Tearing Effect Line Timings
The Tearing Effect signal is described below:
Table 9.13.1 AC characteristics of Tearing Effect Signal Idle Mode Off (Frame Rate = 58.9 Hz) Symbol Parameter min max unit tvdl Vertical Timing Low Duration 13 ms tvdh Vertical Timing High Duration 1000 s thdl Horizontal Timing Low Duration 33 s thdh Horizontal Timing Low Duration 25 500 s NOTE: The timings in Table 9.3.1 apply when MADCTL ML=0 and ML=1 The signal's rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
description
The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid Tearing Effect:
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9.13.3 Example 1: MPU Write is faster than panel read
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the panel scan and each Panel Frame refresh has a complete new image:
Data to be sent
B
Image on LCD
A
A B
B
B
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9.13.4 Example 2: MPU write is slower than panel read
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel Read pointer and finishing download during the subsequent Frame before the Read Pointer "catches" the MPU to Frame memory write position.
B
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9.14 Preset Values
ST7713 will set preset values on our production line for each display module. Any of these preset values do not need customer's SW support.
9.15 Power ON/OFF Sequence
The power on/off sequence is illustrated below:
9.15.1 Uncontrolled Power Off
The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. 2. At an uncontrolled power off the display will go blank and there will not be any visible effects within a few second on the display (blank display) and remains blank until "Power On Sequence" powers it up.
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9.16 Power Level Definition 9.16.1 Power Level
6 level modes are defined they are in order of Maximum Power consumption to Minimum Power Consumption: 1. Normal Mode On (full display), Idle Mode Off, Sleep Out. In this mode, the display is able to show maximum 262,144 colors. 2. Partial Mode On, Idle Mode Off, Sleep Out. In this mode part of the display is used with maximum 262,144 colors. 3. Normal Mode On (full display), Idle Mode On, Sleep Out. In this mode, the full display area is used but with 8 colors. 4. Partial Mode On, Idle Mode On, Sleep Out. In this mode, part of the display is used but with 8 colors. 5. Sleep In Mode In this mode, the DC: DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU interface and memory works with VDDI power supply. Contents of the memory are safe. 6. Power Off Mode In this mode, both VDD and VDDI are removed. Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.
9.16.2 Power Flow Chart
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9.17 Reset Table
Item Frame memory Sleep In/Out Display On/Off Display mode (normal/partial) Display Inversion On/Off Display Idle Mode On/Off Column: Start Address (XS) Column: End Address (XE) Row: Start Address (YS) Row: End Address (YE) Gamma setting RGB for 256, 4k and 65k Color Mode Partial: Start Address (PSL) Partial: End Address (PEL) Scroll: Vertical scrolling Scroll: Top Fixed Area (TFA) Scroll: Scroll Area (VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address (SSA) Tearing: On/Off Tearing Effect Mode (*1) Memory Data Access Control (MY/MX/MV/ML/RGB) After Power On Random In Off Normal Off Off 0000h 007Fh 0000h 007Fh GC0 See Section 9.19 0000h 007Fh Off 0000h 0080h 0000h 0000h Off 0 (Mode1) 0/0/0/0/0 After Hardware Reset No Change In Off Normal Off Off 0000h 007Fh 0000h 007Fh GC0 See Section 9.19 0000h 007Fh Off 0000h 0080h 0000h 0000h Off 0 (Mode1) 0/0/0/0/0 After Software Reset No Change In Off Normal Off Off 0000h 0081h (129d) (when MV=0) 0081h (129d) (when MV=1) 0000h 0081h (129d) (when MV=0) 0081h (129d) (when MV=1) GC0 No Change 0000h 0081h Off 0000h 0082h 0000h 0000h Off 0 (Mode1) No Change No Change 08h No Change No Change 00h 00h 00h NV value NV value
Interface Pixel Color Format 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) RDDPM 08h 08h RDDMADCTL 00h 00h RDDCOLMOD 6 (18-Bit/Pixel) 6 (18-Bit/Pixel) RDDIM 00h 00h RDDSM 00h 00h RDDSDR 00h 00h ID2 NV value NV value ID3 NV value NV value Note1. TE Mode 1 means Tearing Effect Output Line consists of V-Blanking Information only.
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9.18 Module Input/Output Pins 9.18.1 Output or Bi-directional (I/O) Pins
Output or Bi-directional pins After Power On After Hardware Reset After Software Reset TE Low Low Low D7 to D0 (Output driver) High-Z (Inactive) High-Z (Inactive) High-Z (Inactive) Note: There will be no output from D7-D0 during Power On/Off sequence, Hardware Reset and Software Reset.
9.18.2 Input Pins
Input pins RESX CSX D/CX WRX RDX D7 to D0 During Power On Process See 9.15 Input invalid Input invalid Input invalid Input invalid Input invalid After Power On Input valid Input valid Input valid Input valid Input valid Input valid After Hardware Reset Input valid Input valid Input valid Input valid Input valid Input valid After Software Reset Input valid Input valid Input valid Input valid Input valid Input valid During Power Off Process See 9.15 Input invalid Input invalid Input invalid Input invalid Input invalid
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9.18.3 Reset Timing
Table 9.18.3.1 Reset input timing VSS=0V, VDDI=1.65V to 1.95V, VDD=2.6V to 2.9V, Ta = -30 to 70) Symbol Parameter Related Pins MIN TYP tRESW tREST (*1) Reset low pulse width (*2) Reset complete time RESX 10 120 -
MAX -
Note -
Unit us ms
Note 1. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below. Note 2. It will be necessary to wait 120msec before sending next command; this is allowing time for the supply voltages and clock circuits to stabilize. Note 3. During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this period. This loading is done every time when there is H/W reset complete time (tREST) within 120ms after a rising edge of RESX. Note 4. Spike Rejection also applies during a valid reset pulse as shown below:
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9.19 Color Depth Conversion Look Up Tables 9.19.1 65536 Color to 262,144 Color
Color Look Up Table Output Frame Memory Data (6-bits) R005 R004 R003 R002 R001 R000 R015 R014 R013 R012 R011 R010 R025 R024 R023 R022 R021 R020 R035 R034 R033 R032 R031 R030 R045 R044 R043 R042 R041 R040 R055 R054 R053 R052 R051 R050 R065 R064 R063 R062 R061 R060 R075 R074 R073 R072 R071 R070 R085 R084 R083 R082 R081 R080 R095 R094 R093 R092 R091 R090 R105 R104 R103 R102 R101 R100 R115 R114 R113 R112 R111 R110 R125 R124 R123 R122 R121 R120 R135 R134 R133 R132 R131 R130 R145 R144 R143 R142 R141 R140 R155 R154 R153 R152 R151 R150 R165 R164 R163 R162 R161 R160 R175 R174 R173 R172 R171 R170 R185 R184 R183 R182 R181 R180 R195 R194 R193 R192 R191 R190 R205 R204 R203 R202 R201 R200 R215 R214 R213 R212 R211 R210 R225 R224 R223 R222 R221 R220 R235 R234 R233 R232 R231 R230 R245 R244 R243 R242 R241 R240 R255 R254 R253 R252 R251 R250 R265 R264 R263 R262 R261 R260 R275 R274 R273 R272 R271 R270 R285 R284 R283 R282 R281 R280 R295 R294 R293 R292 R291 R290 R305 R304 R303 R302 R301 R300 R315 R314 R313 R312 R311 R310 Default value after H/W Reset 000000 000010 000100 000110 001000 001010 001100 001110 010000 010010 010100 010110 011000 011010 011100 011110 100001 100011 100101 100111 101001 101011 101101 101111 110001 110011 110101 110111 111001 111011 111101 111111 RGBSET Parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Look Up Table Input Data 65k Color (5-bits) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
RED
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Color Look Up Table Output Frame Memory Data (6-bits) G005 G004 G003 G002 G001 G000 G015 G014 G013 G012 G011 G010 G025 G024 G023 G022 G021 G020 G035 G034 G033 G032 G031 G030 G045 G044 G043 G042 G041 G040 G055 G054 G053 G052 G051 G050 G065 G064 G063 G062 G061 G060 G075 G074 G073 G072 G071 G070 G085 G084 G083 G082 G081 G080 G095 G094 G093 G092 G091 G090 G105 G104 G103 G102 G101 G100 G115 G114 G113 G112 G111 G110 G125 G124 G123 G122 G121 G120 G135 G134 G133 G132 G131 G130 G145 G144 G143 G142 G141 G140 G155 G154 G153 G152 G151 G150 G165 G164 G163 G162 G161 G160 G175 G174 G173 G172 G171 G170 G185 G184 G183 G182 G181 G180 G195 G194 G193 G192 G191 G190 G205 G204 G203 G202 G201 G200 G215 G214 G213 G212 G211 G210 G225 G224 G223 G222 G221 G220 G235 G234 G233 G232 G231 G230 G245 G244 G243 G242 G241 G240 G255 G254 G253 G252 G251 G250 G265 G264 G263 G262 G261 G260 G275 G 274 G273 G272 G271 G270 G285 G 284 G283 G282 G281 G280 G295 G 294 G293 G292 G291 G290 G305 G 304 G303 G302 G301 G300 G315 G 314 G313 G312 G311 G310 Default value after H/W Reset 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 RGBSET Parameter 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Look Up Table Input Data 65k Color (5-bits) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111
GREEN
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Color Look Up Table Output Frame Memory Data (6-bits) G325 G324 G323 G322 G321 G320 G335 G334 G333 G332 G331 G330 G345 G344 G343 G342 G341 G340 G355 G354 G353 G352 G351 G350 G365 G364 G363 G362 G361 G360 G375 G374 G373 G372 G371 G370 G385 G384 G383 G382 G381 G380 G395 G394 G393 G392 G391 G390 G405 G404 G403 G402 G401 G400 G415 G414 G413 G412 G411 G410 G425 G424 G423 G422 G421 G420 G435 G434 G433 G432 G431 G430 G445 G444 G443 G442 G441 G440 G455 G454 G453 G452 G451 G450 G465 G464 G463 G462 G461 G460 G475 G474 G473 G472 G471 G470 G485 G484 G483 G482 G481 G480 G495 G494 G493 G492 G491 G490 G505 G504 G503 G502 G501 G500 G515 G514 G513 G512 G511 G510 G525 G524 G523 G522 G521 G520 G535 G534 G533 G532 G531 G530 G545 G544 G543 G542 G541 G540 G555 G554 G553 G552 G551 G550 G565 G564 G563 G562 G561 G560 G575 G574 G573 G572 G571 G570 G585 G584 G583 G582 G581 G580 G595 G594 G593 G592 G591 G590 G605 G604 G603 G602 G601 G600 G615 G614 G613 G612 G611 G610 G625 G624 G623 G622 G621 G620 G635 G634 G633 G632 G631 G630 Default value after H/W Reset 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 RGBSET Parameter 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Look Up Table Input Data 65k Color (5-bits) 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111
GREEN
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Color Look Up Table Output Frame Memory Data (6-bits) B005 B004 B003 B002 B001 B000 B015 B014 B013 B012 B011 B010 B025 B024 B023 B022 B021 B020 B035 B034 B033 B032 B031 B030 B045 B044 B043 B042 B041 B040 B055 B054 B053 B052 B051 B050 B065 B064 B063 B062 B061 B060 B075 B074 B073 B072 B071 B070 B085 B084 B083 B082 B081 B080 B095 B094 B093 B092 B091 B090 B105 B104 B103 B102 B101 B100 B115 B114 B113 B112 B111 B110 B125 B124 B123 B122 B121 B120 B135 B134 B133 B132 B131 B130 B145 B144 B143 B142 B141 B140 B155 B154 B153 B152 B151 B150 B165 B164 B163 B162 B161 B160 B175 B174 B173 B172 B171 B170 B185 B184 B183 B182 B181 B180 B195 B194 B193 B192 B191 B190 B205 B204 B203 B202 B201 B200 B215 B214 B213 B212 B211 B210 B225 B224 B223 B222 B221 B220 B235 B234 B233 B232 B231 B230 B245 B244 B243 B242 B241 B240 B255 B254 B253 B252 B251 B250 B265 B264 B263 B262 B261 B260 B275 B274 B273 B272 B271 B270 B285 B284 B283 B282 B281 B280 B295 B294 B293 B292 B291 B290 B305 B304 B303 B302 B301 B300 B315 B314 B313 B312 B311 B310 Default value after H/W Reset 000000 000010 000100 000110 001000 001010 001100 001110 010000 010010 010100 010110 011000 011010 011100 011110 100001 100011 100101 100111 101001 101011 101101 101111 110001 110011 110101 110111 111001 111011 111101 111111 RGBSET Parameter 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Look Up Table Input Data 65k Color (5-bits) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
BLUE
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9.19.1 4096 Color to 262,144 Color
Color Look Up Table Output Frame Memory Data (6-bits) R005 R004 R003 R002 R001 R000 R015 R014 R013 R012 R011 R010 R025 R024 R023 R022 R021 R020 R035 R034 R033 R032 R031 R030 R045 R044 R043 R042 R041 R040 R055 R054 R053 R052 R051 R050 R065 R064 R063 R062 R061 R060 R075 R074 R073 R072 R071 R070 R085 R084 R083 R082 R081 R080 R095 R094 R093 R092 R091 R090 R105 R104 R103 R102 R101 R100 R115 R114 R113 R112 R111 R110 R125 R124 R123 R122 R121 R120 R135 R134 R133 R132 R131 R130 R145 R144 R143 R142 R141 R140 R155 R154 R153 R152 R151 R150 R165 R164 R163 R162 R161 R160 | R315 R314 R313 R312 R311 R310 Default value after H/W Reset 000000 000100 001000 001100 010001 010101 011001 011101 100010 100110 101010 101110 110011 110111 111011 111111 -----| -----RGBSET Parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | 32 Look Up Table Input Data 4k Color (4-bits) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not used
RED
Color
Look Up Table Output Frame Memory Data (6-bits) G005 G004 G003 G002 G001 G000 G015 G014 G013 G012 G011 G010 G025 G024 G023 G022 G021 G020 G035 G034 G033 G032 G031 G030 G045 G044 G043 G042 G041 G040 G055 G054 G053 G052 G051 G050 G065 G064 G063 G062 G061 G060 G075 G074 G073 G072 G071 G070 G085 G084 G083 G082 G081 G080 G095 G094 G093 G092 G091 G090 G105 G104 G103 G102 G101 G100 G115 G114 G113 G112 G111 G110 G125 G124 G123 G122 G121 G120 G135 G134 G133 G132 G131 G130 G145 G144 G143 G142 G141 G140 G155 G154 G153 G152 G151 G150 G165 G164 G163 G162 G161 G160 | G635 G634 G633 G632 G631 G630
Default value after H/W Reset 000000 000100 001000 001100 010001 010101 011001 011101 100010 100110 101010 101110 110011 110111 111011 111111 -----| ------
RGBSET Parameter 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 | 96
GREEN
Look Up Table Input Data 4k Color (4-bits) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not used
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Color Look Up Table Output Frame Memory Data (6-bits) B005 B004 B003 B002 B001 B000 B015 B014 B013 B012 B011 B010 B025 B024 B023 B022 B021 B020 B035 B034 B033 B032 B031 B030 B045 B044 B043 B042 B041 B040 B055 B054 B053 B052 B051 B050 B065 B064 B063 B062 B061 B060 B075 B074 B073 B072 B071 B070 B085 B084 B083 B082 B081 B080 B095 B094 B093 B092 B091 B090 B105 B104 B103 B102 B101 B100 B115 B114 B113 B112 B111 B110 B125 B124 B123 B122 B121 B120 B135 B134 B133 B132 B131 B130 B145 B144 B143 B142 B141 B140 B155 B154 B153 B152 B151 B150 B165 B164 B163 B162 B161 B160 | B315 B314 B313 B312 B311 B310 Default value after H/W Reset 000000 000100 001000 001100 010001 010101 011001 011101 100010 100110 101010 101110 110011 110111 111011 111111 -----| -----RGBSET Parameter 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 | 128 Look Up Table Input Data 4k Color (4-bits) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not used
BLUE
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9.20 Sleep Out-Command and Self-Diagnostic Functions of the Display Module 9.20.1 Register Loading Detection
Sleep Out-command (See section 10.1.12 "Sleep Out (11h)") is a trigger for an internal function of the display module, which indicates, if the display module loading function of factory default values from EEPROM (or similar device) to registers of the display controller is working properly. There are compared factory values of the EEPROM and register values of the display controller by the display controller. If those both values (EEPROM and register values) are same, there is inverted (=increased by 1) a bit, which is defined in command 10.1.10 "Read Display Self-Diagnostic Result (0Fh)" (=RDDSDR) (The used bit of this command is D7). If those both values are not same, this bit (D7) is not inverted (= increased by 1). The flow chart for this internal function is following:
Power on sequence HW reset SW reset
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
RDDSDR's D7=0
Sleep Out (11h)
Loads values from EEPROM to registers
Compares EEPROM and register values
No
Are EEPROM and register values same ?
Yes D7 inverted
Note: There is not compared and loaded register values, which can be changed by user (00h to AFh and DAh to DDh), by the display module.
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9.20.2 Functionality Detection
Sleep Out-command (See section 10.1.12 "Sleep Out (11h)") is a trigger for an internal function of the display module, which indicates, if the display module is still running and meets functionality requirements. The internal function (= the display controller) is comparing, if the display module is still meeting functionality requirements (only Booster voltage level). If functionality requirement is met, there is inverted (= increased by 1) a bit, which defined in command 10.1.10 "Read Display Self- Diagnostic Result (0Fh)" (= RDDSDR) (The used bit of this command is D6). If functionality requirement is not same, this bit (D6) is not inverted (= increased by 1). The flow chart for this internal function is following:
Power on sequence HW reset SW reset
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
RDDSDR's D6=0
Sleep Out (11h)
Checks Booster voltage levels and other functionalities
No
Is functionality requirement met?
Yes D6 inverted
Note: There is needed 120msec after Sleep Out -command, when there is changing from Sleep In -mode to Sleep Out -mode, before there is possible to check if functionality requirements are met and a value of RDDSDR's D6 is valid. Otherwise, there is 120msec delay for D6's value, when Sleep Out -command is sent in Sleep Out -mode.
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9.20.3 Chip Attachment Detection
Sleep Out-command (See section 10.1.12 "Sleep Out (11h)") is a trigger for an internal function of the display module, which indicates, if a chip or chips (e.g. driver, etc.) of the display module is/are attached to the circuit route of a flex foil or display glass ITO. There is inverted (= increased by 1) a bit, which is defined in command 10.1.10 "Read Display Self- Diagnostic Result (0Fh)" (= RDDSDR) (The used bit of this command is D5), if the chip or chips is/are attached to the circuit route of the flex or display glass. If this chip is or those chips are not attached to the circuit route of the flex or display glass, this bit (D5) is not inverted (= increased by 1). The following figure is for reference purposes; how this chip attachment can be implemented e.g. there are connected together 2 bumps via route of ITO or the flex foil on 4 corners of the driver (chip).
Bump Routing Between bumps
Through view of driver to bumps
Routing Between bumps
Substrate of display glass
The flow chart for this internal function is following:
Power on sequence HW reset SW reset
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
RDDSDR's D5=0
Sleep Out (11h)
Checks, if chip is attached to route
No Is chip attached to routes?
Yes D5 inverted
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9.20.4 Display Glass Break Detection
Sleep Out-command (See section 10.1.12 "Sleep Out (11h)") is a trigger for an internal function of the display module, which indicates, if the display glass of the display module is broken or not. There is inverted (= increased by 1) a bit, which is defined in command 10.1.10 "Read Display Self-Diagnostic Result (0Fh)" (= RDDSDR) (The used bit of this command is D4), if the display glass is not broken. If this display glass is broken, this bit (D4) is not inverted (= increased by 1). The following figure is a reference, how this glass break detection can be implemented e.g. there is connected together 2 bumps via route of ITO. This route of ITO is the nearest route of the edge of the display glass.
Active area of the display glass
Through view of driver to Bump
Substrate of display glass
The flow chart for this internal function is following:
Power on sequence HW reset SW reset
Sleep In (10h)
Sleep Out Mode
Sleep In Mode
RDDSDR's D4=0
Sleep Out (11h)
Checks, if display glass broken
No Is the display glass broken?
Yes D4 inverted
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9.21 External Light Source
The operation of the module can meet customer's Environmental reliability requirements.
9.22 Oscillator
The chip has on-chip oscillator that does not require external components. This oscillator output signal is used for system clock generation for internal display operation.
9.23 System Clock Generator
The timing generator produces the various signals to driver the internal circuitty. Internal chip operation is not affected by operations on the data bus.
9.24 Instruction Decoder and Register
The instruction decoder indentifies command words arriving at the interface and routes the following data bytes to their destination. The command set can be found in "Command" section.
9.25 Source Driver
The source driver block includes 132x3 source outputs (S1 to S396), which should be connected directly to the TFT-LCD. The source output signals are generated in the data processing block after the data is read out of the RAM and latched, which represent the simulatance selected rows.
9.26 Gate Driver
The gate driver block includes 132 channel gate output (G1 to G132) which should be connected directly to the TFT-LCD.
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10. Command 10.1 System function Command List and Description
Table 10.1.1 System Function command List (1)
Instruction NOP SWRESET Refer D/CX WRX RDX D17-8 10.1.1 10.1.2 0 0 0 1 RDDID 10.1.3 1 1 1 0 1 RDDST 10.1.4 1 1 1 1 0 RDDPM 10.1.5 1 1 0 RDD MADCTL 10.1.6 1 1 0 RDD COLMOD 10.1.7 1 1 0 RDDIM 10.1.8 1 1 0 RDDSM 10.1.9 1 1 0 RDDSDR 10.1.10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 0 0 0 ID17 1 ID37 0 BSTON D6 0 0 0 ID16 ID26 ID36 0 MY D5 0 0 0 ID15 ID25 ID35 0 MX D4 0 0 0 ID14 ID24 ID34 0 MV IFPF0 ST21 0 0 ML 0 VIP0 0 0 0 BRD D3 0 0 0 ID13 ID23 ID33 1 ML D2 0 0 1 ID12 ID22 ID32 0 RGB D1 0 0 0 ID11 ID21 ID31 0 D0 0 1 0 ID10 ID20 ID30 1 ST24 (Hex) (00h) No Operation (01h) Software reset (04h) Read Display ID Dummy read ID1 read ID2 read ID3 read (09h) Read Display Status Dummy read (0Ah) Read Display Power Mode Dummy read (0Bh) Read Display MADCTL Dummy read (0Ch) Read Display Pixel Format Dummy read (0Dh) Read Display Image Mode Dummy read (0Eh) Read Display Signal Mode Dummy read (0Fh) Read Display Self-diagnostic result Dummy rea Function
ST23 IFPF2 IFPF1 VSSON ST14 INVON 0 0 MY 0 0 VSSON 0 0 0 0 MX 0 0 D6 0 0 0 0 MV 0 0 INVON 0 0 -
IDMON PTLON SLOUT NORON ST11 DISON TEON GCS2 VSON PCKON DEON 1 1 RGB 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 ST0 0 1 0 1 0 1 -
GCS1 GCS0 TELON HSON
BSTON IDMON PTLON SLPOUT NORON DISON
VIPF3 VIPF2 VIPF1
IFPF2 IFPF1 IFPF0
GCS2 GCS1 GCS0
TEON TELON HSON VSON PCKON DEON
RELD FUND ATTD
"-": Don't care
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Table 10.1.2 System Function command List (2)
Instruction Refer D/CX WRX RDX D17-8 D7 SLPIN SLPOUT PTLON NORON INVOFF INVON GAMSET DISPOFF DISPON 10.1.11 10.1.12 10.1.13 10.1.14 10.1.15 10.1.16 10.1.17 10.1.18 10.1.19 0 0 0 0 0 0 0 1 0 0 0 1 CASET 10.1.20 1 1 1 0 1 1 RASET 10.1.21 1 1 RAMWR 10.1.22 0 1 0 RAMRD 10.1.23 1 1 "-": Don't care 1 1 1 1 1 1 1 YE7 0 D7 0 D7 YE6 0 D6 0 D6 YE5 1 D5 1 D5 YE4 0 D4 0 D4 YE3 1 D3 1 D3 YE2 1 D2 1 D2 YE1 0 D1 1 D1 YE0 0 D0 0 D0 (2Ch) Memory write Write data (2Eh) Memory read Dummy read Read data Y address end:SYEY 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 XS7 XE7 0 YS7 D6 0 0 0 0 0 0 0 0 0 0 XS6 XE6 0 YS6 D5 0 0 0 0 1 1 1 1 1 1 XS5 XE5 1 YS5 D4 1 1 1 1 0 0 0 0 0 0 XS4 XE4 0 YS4 D3 0 0 0 0 0 0 0 1 1 1 XS3 XE3 1 YS3 D2 0 0 0 0 0 0 1 0 0 0 XS2 XE2 0 YS2 D1 0 0 1 1 0 0 1 0 0 1 XS1 XE1 1 YS1 D0 0 1 0 1 0 1 0 0 1 0 XS0 (Hex) Function (10h) Sleep in & booster off (11h) Sleep out & booster on (12h) Partial mode on (13h) Partial off (Normal) Display inversion off (normal) (21h) Display inversion on (20h) (26h) Gamma curve select (28h) Display off (29h) Display on (2Ah) Column address set X address start: 0SX
GC3 GC2 GC1 GC0
X address end: XSXEX XE0 1 (2Bh) Row address set YS0 Y address start: 0YSY
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Table 10.1.3 System Function command List (3)
Instruction Refer D/CXWRXRDX D17-8 D7 0 1 1 1 1 0 1 1 1 1 1 1 0 0 1 0 1 0 1 1 0 0 0 1 0 RDID1 10.1.34 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D6 D5 D4 D3 D2 D1 D0 0 PSL0 PEL0 1 TFA0 VSA0 BFA0 0 1 (Hex) Function 0 0 1 1 0 0 0 PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 0 0 1 1 0 0 1 TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 (30h) Partial start/end address set Partial start address (0,1,2, ..P) Partial end address (0,1,2, .., P) (33h) Scroll area set Top fixed area (0,1,2, .., S) Vertical scroll area (0,1,2, .., S) Bottom fixed area (0,1,2, .., S)
PTLAR
10.1.25
SCRLAR 10.1.26
TEOFF TEON
10.1.27 10.1.28
MADCTL 10.1.29
VSCSAD 10.1.30 IDMOFF 10.1.31 IDMON 10.1.32 COLMOD 10.1.33
(34h) Tearing effect line off (35h) Tearing effect mode set & on Mode1: TELOM="0" - TELOM Mode2: TELOM="1" 0 0 1 1 0 1 1 0 (36h) Memory data access control MY MX MV ML RGB 0 0 1 1 0 1 1 1 (37h) Scroll start address of RAM SSA = 0, 1, 2, ..., 131 SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0 0 0 1 1 1 0 0 0 (38h) Idle mode off 0 0 1 1 1 0 0 1 (39h) Idle mode on 0 0 1 1 1 0 1 0 (3Ah) Interface pixel format VIPF3 VIPF2VIPF1 VIPF0 - IFPF2IFPF1 IFPF0 Interface format 1 1 0 1 1 0 1 0 (DAh) Read ID1 Dummy read
RDID2
10.1.35
ID17 ID16 ID15 ID14 ID13 ID12 ID11 1 1 0 1 1 0 1 1 ID26 ID25 ID24 ID23 ID22 ID21 1 1 0 1 1 1 0 ID37 ID36 ID35 ID34 ID33 ID32 ID31
ID10 Read parameter 1 (DBh) Read ID2 Dummy read ID20 Read parameter 0 (DCh) Read ID3 ID30 Dummy read Read parameter
RDID3
10.1.36
"-": Don't care Note 1: After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer "RESET TABLE" section) Note 2: Undefined commands are treated as NOP (00 h) command. Note 3: B0 to D9 and DA to F are for factory use of driver supplier. Note 4: Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML parameter only), 37h, 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTL (0Bh), Read Display Pixel Format (0Ch), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh) and Read Display Self Diagnostic Result (0Fh) of these commands are updated immediately both in Sleep In mode and Sleep Out mode.
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10.2 Panel Function Command List and Description
Table 10.2.1 Panel Function Command List (1)
Instruction Refer D/CX WRX RDX D17-8 0 RGBCTR 10.2.1 1 1 0 0 DISSW ICM DP EP HSP VSP 1 D7 1 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0
(Hex) Function (B0h)
Set RGB signal control ICM: RGB data ascess select DW RGB interface bus width set DP, HSP, VSP: PCLK, HS, VS polarity set In normal mode (Full colors) RTNA set 1-line period FPA: front porch BPA: back porch
0 FRMCTR1 10.2.2 1 1 1 0 FRMCTR2 10.2.3 1 1 1 0 1 FRMCTR3 10.2.4 1 1 1 1 1 0 INVCTR 10.2.5 1 0 RGB PRCTR 10.2.6 1 1 1 1 0 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
-
1
0
1
1
0
0
0
1
(B1h)
RTNA3 RTNA2 RTNA1 RTNA0 FPA3 BPA3 1 0 1 1 0 FPA2 BPA2 0 FPA1 BPA1 1 FPA0 BPA0 0
(B2h)
In Idle mode (8-colors) RTNB: set 1-line period FPB: front porch BPB: back porch In partial mode + Full colors
RTNB3 RTNB2 RTNB1 RTNB0 FPB3 FPB2 FPB1 FPB0 BPB3 1 0 1 1 0 BPB2 0 BPB1 1 BPB0 1
(B3h)
RTNC3 RTNC2 RTNC1 RTNC0 FPC3 BPC3 RTND3 FPD3 BPD3 1 0 1 0 0 0 1 0 1 1 0 1 0 0 0 FPC2 BPC2 RTND2 FPD2 BPD2 1 NLA 1 VBP2 HBP2 1 SDT0 FPC1 BPC1 RTND1 FPD1 BPD1 0 NLB 0 VBP1 HBP1 1 EQ1 FPC0 BPC0 RTND0 FPD0 BPD0 0 NLC 1 VBP0 HBP8 HBP0 0 EQ0
(B6h)
Display function setting NO: the amount of non-overlap SDT: set amount of source delay EQ: set EQ period PT: No display area source/VCOM/Gate output control RTNC,RTND: set 1-line period FPC,FPD: front porch BPC,BPD: back porch
(B4h)
Display inversion control NLA,NLB,NLC set inversion RGB I/F Blanking porch setting
(B5h)
VBP7 VBP6 VBP5 VBP4 VBP3 HBP7 HBP6 HBP5 HBP4 HBP3 1 0 0 0 1 NO1 1 NO0 0 SDT1
DISSET5
10.2.7
1
1
0
0
0
0
PTG1
PTG0
PT1
PT0
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Table 10.2.2 Panel Function Command List (2)
Instruction Refer D/CX WRX RDX D17-8 0 1 1 1 PWCTR1 10.2.8 1 0 PWCTR2 10.2.9 1 0 PWCTR3 10.2.10 1 1 0 PWCTR4 10.2.11 1 1 0 PWCTR5 10.2.12 1 1 0 VMCTR1 10.2.13 1 1 VMOFCTR 10.2.1 4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 1 D6 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 D3 D2 D1 D0 (Hex) Function 0 0 0 0 0 (C0h) Power control setting VRH: Set the GVDD VRH4 VRH3 VRH2 VRH1 VRH0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VC2 0 BT2 0 APA2 0 DCA2 0 0 APB2 0 DCB2 0 1 VC1 0 BT1 1 APA1 0 DCA1 0 1 APB1 0 DCB1 0 0 VC0 1 BT0 0 (C2h)
voltage VC: Set the VCI1 voltage
(C1h) Power control setting
BT: set AVDD/VCL/VGH/ VGL voltage In normal mode (Full colors)
APA0 APA: adjust the operational 0 amplifier DCA: adjust the booster DCA0 circuit for Idle mode 0 1 (C3h) In Idle mode (8-colors) APB0 APB: adjust the operational amplifier 0 DCB: adjust the booster DCB0 circuit for Idle mode 0 0 (C4h) In partial mode + Full colors
APC: adjust the operational amplifier DCC: adjust the booster circuit for Idle mode
APC2 APC1 APC0 DCC2 DCC1 DCC0 1 0 1
(C5h) VCOM control 1
VMH: VCOMH voltage control VML: VCOML voltage control
VMH6 VMH 5 VMH4 VMH3 VMH2 VMH1 VMH0 VML6 VML5 VM 4 VML3 VML2 VML1 VML0 1 VMF6 0 0 0 1 1 1
(C7h) VCOM offset control
VMF3 VMF2 VMF1 VMF0
"-": Don't care Note 1: C0h to C7h are fixed for about power controller.
Table 10.2.3 Panel Function Command List (3)
Instruction Refer D/CX WRXRDX D17-8 0 1 WRID2 10.2.15 1 1 0 WRID3 10.2.16 1 0 1 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D7 1 0 1 ID37 1 ID417 ID427 ID437 ID447 1 1 1 0 1 1 0 1 0 D6 1 ID26 1 ID36 1 ID416 ID426 ID436 ID446 1 1 0 0 0 1 1 1 1 D5 0 ID25 0 ID35 0 ID415 ID425 ID435 ID445 0 0 1 0 1 0 0 1 0 D4 1 ID24 1 ID34 1 ID414 ID424 ID434 ID444 1 EXTC 1 0 0 0 1 1 1 1 D3 0 D2 0 D1 0 ID21 1 ID31 1 ID411 ID421 ID431 ID441 0 1 1 1 0 1 0 0 1 D0 1 ID20 0 ID30 1 ID410 ID420 ID430 ID440 1 RDY 0 0 1 1 1 1 0 0 (D3h) (D2h) (Hex) Function (D1h) LCM version code
Write ID2 value to NV memory Set the LCM version code at ID2 Customer Project code Write ID3 value to NV memory Set the project code at ID3 IC Vender Coder Dummy read ID41:IC Vender Code ID42: IC Part Number Code ID43 & ID44: Chip version coder
ID23 ID22 0 0
ID33 ID32 0 0 ID413 ID412 ID423 ID422 ID433 ID432 ID443 ID442 1 0 1 1 1 0 1 1 0 1 1 1 0 1 0 0 1 0
RDID4
10.2.17
NVCTR1 10.2.18
(D9h) OTP control status (DEh) OTP read command AA 0F A5 (DFh) OTP write command 55 F0 5A
NVCTR2 10.2.19
NVCTR3 10.2.20
"-": Don't care Note 1: The D1h to D3h registers are fixed for about ID code setting. Note 2: The D9h, DEh and DFh registers are used for NV Memory function controller. (Ex: write, clear, etc.)
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Table 10.2.4 Panel Function Command List (4)
Instruction Refer D/CX WRXRDX D17-8 D7 D6 0 1 1 1 1 1 1 GAMCTRP1 10.2.21 1 1 1 1 1 1 1 0 1 1 1 1 1 1 GAMCTRN1 10.2.22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PKN53 PKN52 PKN51 PKN50 PKN63 PKN62 PKN61 PKN60 PKN73 PKN72 PKN71 PKN70 PKN83 PKN82 PKN81 PKN80 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PKP53 PKP52 PKP51 PKP50 PKP63 PKP62 PKP61 PKP60 PKP73 PKP72 PKP71 PKP70 PKP83 PKP82 PKP81 PKP80 1 1 1 1 1 1 1 1 1 D5 1 D4 0 D3 0 RFP3 D2 0 RFP2 D1 0 RFP1 D0 0 RFP0 (Hex) Function (E0h) Set Gamma correction
Gamma adjustment (+ polarity)
PKP04 PKP03 PKP02 PKP01 PKP00 PKP14 PKP13 PKP12 PKP11 PKP10 PKP24 PKP23 PKP22 PKP21 PKP20 PKP34 PKP33 PKP32 PKP31 PKP30 PKP44 PKP43 PKP42 PKP41 PKP40
RFP14 RFP13 RFP12 RFP11 RFP10 OSP14 OSP13 OSP12 OSP11 OSP10 0 OSP3 0 RFN3 OSP2 0 RFN2 OSP1 0 RFN1 OSP0 0 RFN0 (E1h) Set Gamma correction
Gamma adjustment (- polarity)
PKN04 PKN03 PKN02 PKN01 PKN00 PKN14 PKN13 PKN12 PKN11 PKN10 PKN24 PKN23 PKN22 PKN21 PKN20 PKN34 PKN33 PKN32 PKN31 PKN30 PKN44 PKN43 PKN42 PKN41 PKN40
RFN14 RFN13 RFN12 RFN11 RFN10 OSN14 OSN13 OSN12 OSN11 OSN10 OSN3 OSN2 OSN1 OSN0
"-": Don't care Note 1: E0-E1 registers are fixed for about Gamma adjustment.
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10.1.1 NOP (00h)
00H Inst / Para NOP Parameter D/CX WRX RDX 0 1 D17-8 D7 0 NOP (No Operation) D6 D5 D4 D3 0 0 0 0 No Parameter D2 0 D1 0 D0 0 (Code) (00h) -
NOTE: "-" Don't care
Description -This command is empty command.
10.1.2 SWRESET (01h): Software Reset
01H Inst / Para SWRESET Parameter
NOTE: "-" Don't care
D/CX WRX RDX 0 1
D17-8 -
D7 0
SWRESET (Software Reset) D6 D5 D4 D3 0 0 0 0 No Parameter
D2 0
D1 0
D0 1
(Code) (01h) -
-If Software Reset is applied during Sleep In mode, it will be necessary to wait 120msec before sending next command. Description -The display module loads all default values to the registers during 120msec. -If Software Reset is applied during Sleep Out or Display On Mode, it will be necessary to wait 120msec before sending next command.
10.1.3 RDDID (04h): Read Display ID
04H Inst / Para
RDDID (Read Display ID)
D/CX WRX RDX 0 1 1 1 1 1 1 1 1 1 D17-8 D7 0 ID17 1 ID37 D6 0 ID16 ID26 ID36 D5 0 ID15 ID25 ID35 D4 0 ID14 ID24 ID34 D3 0 ID13 ID23 ID33 D2 1 ID12 ID22 ID32 D1 0 ID11 ID21 ID31 D0 0 ID10 ID20 ID30 (Code) (04h) -
RDDID 1st Parameter 2nd Parameter 3rt Parameter 4th Parameter
NOTE: "-" Don't care
-This read byte returns 24-bit display identification information. -The 1st parameter is dummy data -The 2nd parameter (ID17 to ID10): LCD module's manufacturer ID. Description -The 3rd parameter (ID26 to ID20): LCD module/driver version ID -The 4th parameter (ID37 to UD30): LCD module/driver ID.
NOTE: Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h, respectively. Status Default Value ID1 ID2 8xh 8xh 8xh ID3 00h 00h 00h
Default
Power On Sequence S/W Reset H/W Reset
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10.1.4 RDDST (09h): Read Display Status
09H Inst / Para RDDST
1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 5th Parameter
NOTE: "-" Don't care
D/CX WRX RDX 0 1
1 1 1 1 1 1 1 1 1 1

D17-8 -
D7 0
-
RDDST (Read Display Status) D6 D5 D4 D3 0 0 0 1
MY IFPF2 ST14 GCS0
D2 0
-
D1 0
-
D0 1
ST24
NORON
(Code) (09h)
-
MX IFPF1 INVON TELOM
MV IFPF0 ST12 HSON
-
-
BSTON ST23 VSSON GCS1
ML RGB IDMON PTLON SLOUT ST11 DISON TEON VSON PCKON DEON
GCS2 ST0
This command indicates the current status of the display as described in the table below:
Bit BSTON MY MX MV ML Description Booster Voltage Status Row Address Order (MY) Column Address Order (MX) Row/Column Exchange (MV) Scan Address Order (ML) Value `1' =Booster on, `0' =Booster off `1' =Decrement, (Bottom to Top, when MADCTL (36h) D7='1') `0' =Increment, (Top to Bottom, when MADCTL (36h) D7='0') `1' =Decrement, (Right to Left, when MADCTL (36h) D6='1') `0' =Increment, (Left to Right, when MADCTL (36h) D6='1') `1' = Row/column exchange, (when MADCTL (36h) D5='1') `0' = Normal, (when MADCTL (36h) D5='0') `1' =Decrement, (LCD refresh Top to Bottom, when MADCTL (36h) D4='1') `0'=Increment, (LCD refresh Bottom to Top, when MADCTL (36h) D4='0') `1' =BGR, (When MADCTL (36h) D3='1') `0' =RGB, (When MADCTL (36h) D3='0') `0' `0' "011" = 12-bit / pixel, "101" = 16-bit / pixel, "110" = 18-bit / pixel, others are no define `1' = On, "0" = Off `1' = On, "0" = Off `1' = Out, "0" = In `1' = Normal Display, `0' = Partial Display `1' = Scroll on,"0" = Scroll off `0' `1' = On, "0" = Off `0' `0' `1' = On, "0" = Off `1' = On, "0" = Off "000" = GC0 "001" = GC1 "010" = GC2 "011" = GC3 "100" to "111" = Not defined `0' = mode1, `1' = mode2 `1' = On, `0' = Off
RGB ST24 ST23 IFPF2 IFPF1 IFPF0 IDMON PTLON SLPOUT NORON VSSON ST14 INVON ST12 ST11 DISON TEON GCSEL2 GCSEL1 GCSEL0 TELOM HSON
RGB/ BGR Order (RGB) For Future Use For Future Use Interface Color Pixel Format Definition Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Vertical Scrolling Status Horizontal Scroll Status Inversion Status All Pixels On (Not Used) All Pixels Off (Not Used) Display On/Off Tearing effect line on/off
Description
Gamma Curve Selection
Tearing effect line mode Horizontal Sync. (HS, RGB I/F) VSON Vertical Sync, (VS, RGB I/F) `1' = On, `0' = Off PCLKON Pixel Clock (PCLK, RGB I/F) `1' = On, `0' = Off DEON Data Enable (DE, RGB I/F) `1' = On, `0' = Off ST0 For Future Use `0' Note: ST0, ST5, ST9, ST11-ST15, ST19, ST23, ST24 are set to `0', when RGB I/F. Status
Default
Power On Sequence S/W Reset H/W Reset
ST[31-24] 0000-0000 0xxx0xx00 0000-0000
Default Value (ST31 to ST0) ST[23-16] ST[15-8] 0110-0001 0000-0000 0xxx-0001 0000-0000 0110-0001 0000-0000
ST[7-0] 0000-0000 0000-0000 0000-0000
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10.1.5 RDDPM (0Ah): Read Display Power Mode
0AH Inst / Para RDDPM
1st Parameter 2nd Parameter
D/CX WRX RDX 0 1
1 1 1 1
D17-8 -
RDDPM (Read Display Power Mode) D7 D6 D5 D4 D3 0 0 0 0 1
-
D2 0
-
D1 1
-
D0 0
-
(Code) (0Ah)
-

BSTON IDMON PTLON SLPOUT NORON DISON
D1
D0
NOTE: "-" Don't care, can be set to VDDI or DGND level
This command indicates the current status of the display as described in the table below:
Bit
BSTON IDMON
Description
Booster Voltage Status Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Display On/Off Not Used Not Used Status Power On Sequence S/W Reset H/W Reset `1' =Booster on, `0' =Booster off `1' = Idle Mode On, `0' = Idle Mode Off `1' = Partial Mode On, `0' = Partial Mode Off `1' = Sleep Out, `0' = Sleep In `1' = Normal Display, `0' = Partial Display `1' = Display On, `0' = Display Off `0' `0'
Value
Description
PTLON SLPON NORON DISON D1 D0
Default
Default Value (D7 to D0) 0000_1000(08h) 0000_1000(08h) 0000_1000(08h)
10.1.6 RDDMADCTL (0Bh): Read Display MADCTL
0BH Inst / Para RDDMADCTL
1st Parameter 2nd Parameter
D/CX 0
1 1
WRX
RDX 1

RDDMADCTL (Read Display MADCTL) D17-8 D7 D6 D5 D4 D3 0 0 0 0 1 MY MX MV ML RGB
D2 0
-
D1 1
D1
D0 1
D0
(Code) (0Bh)
-
1 1
NOTE: "-" Don't care, can be set to VDDI or DGND level
This command indicates the current status of the display as described in the table below:
Bit MY MX Description Row Address Order Column Address Order Row/Column Order (MV) Vertical Refresh Order RGB/BGR Order Not Used Not Used Value `1' = Bottom to Top (When MADCTL B7='1') `0' = Top to Bottom (When MADCTL B7='0') `1' = Right to Left (When MADCTL B6='1') `0' = Left to Right (When MADCTL B6='0') `1' = Row/column exchange (MV=1) `0' = Normal (MV=0) `1' =LCD Refresh Bottom to Top `0' =LCD Refresh Top to Bottom `1' =BGR, "0"=RGB `0' `0'
Description
MV ML RGB D1 D0
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value (D7 to D0) 0000_0000 (00h) No change 0000_0000 (00h)
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10.1.7 RDDCOLMOD (0Ch): Read Display Pixel Format
0CH Inst / Para RDDCOLMOD
1st Parameter 2nd Parameter
D/CX 0
1 1
WRX
RDX 1

D17-8 -
RDDCOLMOD (Read Display Pixel Format) D7 D6 D5 D4 D3 D2 0 0 0 0 1 1
VIPF3 VIPF2 VIPF1 VIPF0 IFPF2
D1 0
IFPF1
D0 0
IFPF0
(Code) (0Ch)
-
1 1
NOTE: "-" Don't care, can be set to VDDI or DGND level
This command indicates the current status of the display as described in the table below:
IFPF[2:0] 011 101 110 111 3 5 6 7 MCU Interface Color Format 12-bit/pixel 16-bit/pixel 18-bit/pixel No used
Description Others are no define and invalid
VIFPF[2:0] 0101 0110 0111 1110 5 6 7 14 RGB Interface Color Format 16-bit/pixel (1-times data transfer) 18-bit/pixel (1-times data transfer) No used 18-bit/pixel (3-times data transfer)
Others are no define and invalid
Status Default Value IFPF[2:0] 0110 (18 bits/pixel) No Change 0110 (18 bits/pixel) VIPF[3:0] 0110 (18 bits/pixel) No Change 0110 (18 bits/pixel)
Default
Power On Sequence S/W Reset H/W Reset
10.1.8 RDDIM (0Dh): Read Display Image Mode
0DH Inst / Para RDDIM
1st Parameter 2nd Parameter
D/CX WRX RDX 0 1
1 1 1 1

D17-8 -
RDDIM (0Dh): Read Display Image Mode D7 D6 D5 D4 D3 D2 0 0 0 0 1 1
VSSON
D1 0
GCS1
D0 1
GCS0
(Code) (0Dh)
-
D6
INVON
D4
D3
GCS2
NOTE: "-" Don't care, can be set to VDDI or DGND level This command indicates the current status of the display as described in the table below: Bit VSSON D6 Description Vertical Scrolling On/Off Horizontal Scrolling On/Off Inversion On/Off All Pixels On All Pixels Off Gamma Curve Selection Value "1" = Vertical scrolling is On, "0" = Vertical scrolling is Off "0" (Not used) "1" = Inversion is On, "0" = Inversion is Off "0" (Not used) "0" (Not used) "000" = GC0, "001" = GC1, "010" = GC2, "011" = GC3, "100" to "111" = Not defined Default Value(D7 to D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h)
Description
INVON D4 D3 GCS2 GCS1 GCS0
Default
Status Power On Sequence S/W Reset H/W Reset
Ver 1.6
107
2008-05
ST7713
10.1.9 RDDSM (0Eh): Read Display Signal Mode
0EH Inst / Para RDDSM
1st Parameter 2
nd
RDDSM (0Eh): Read Display Signal Mode D/CX WRX 0
1 1 1 1
RDX 1

D17-8 -
D7 0
TEON
D6 0
TELOM
D5 0
HSON
D4 0
VSON
D3 1
PCKON
D2 1
DEON
D1 1
D1
D0 0
D0
(Code) (0Eh)
-
Parameter
NOTE: "-" Don't care, can be set to VDDI or DGND level
This command indicates the current status of the display as described in the table below:
Bit TEON TELOM HSON Description Tearing Effect Line On/Off Tearing effect line mode Horizontal Sync. (RGB I/F) On/Off Vertical Sync. (RGB I/F) On/Off Pixel Clock (PCLK, RGB I/F) On/Off Data Enable (DE, RGB I/F) On/Off Not Used Not Used Status Power On Sequence S/W Reset H/W Reset "1" = On, "0" = Off "1" = mode1, "0" = mode2 "1" = On, "0" = Off "1" = On, "0" = Off "1" = On, "0" = Off "1" = On, "0" = Off "1" = On, "0" = Off "1" = On, "0" = Off Default Value(D7~D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h) Value
Description
VSON PCKON DEON D1 D0
Default
10.1.10 RDDSDR (0Fh): Read Display Self-Diagnostic Result
0FH Inst / Para RDDSDR
1st Parameter 2nd Parameter
D/CX 0
1 1
WRX
RDX 1

RDDSDR (0Fh): Read Display Self-Diagnostic Result D17-8 D7 D6 D5 D4 D3 D2 0 0 0 0 1 1
RELD FUND ATTD BRD D3 D2
D1 1
D1
D0 1
D0
(Code) (0Fh)
-
1 1
NOTE: "-" Don't care, can be set to VDDI or DGND level
This command indicates the current status of the display as described in the table below:
Bit RELD FUND ATTD BRD D3 D2 D1 D0 Description Register Loading Detection Functionality Detection Chip Attachment Detection Display Glass Break Detection Not Used Not Used Not Used Not Used Status Power On Sequence S/W Reset H/W Reset Value See section 9.20 See section 9.20 See section 9.20 See section 9.20 "0" "0" "0" "0" Default Value(D7~D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h)
Description
Default
Ver 1.6
108
2008-05
ST7713
10.1.11 SLPIN (10h): Sleep In
10H Inst / Para SLPIN st 1 Parameter D/CX 0 WRX
RDX 1
D17-8 -
SLPIN (Sleep In) D7 D6 D5 D4 0 0 0 1 No parameter
D3 0
D2 0
D1 0
D0 0
(Code) (10h) -
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command causes the LCD module to enter the minimum power consumption mode. -In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped.
Sleep In VDDI VDD Gate Output Source Output 0V 0V Blanking display (over 1frame display) * 0V STOP STOP DISCHARGE 0V or VDD 0V or VDD 0V 0V or VDD 0V 1.6V-3.0V 2.6V-3.0V STOP
VCOM Output
Description
Internal counter Internal Oscillator DC charge in capacitors VGH VGL AVDD IC Internal reset
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
-This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by the Sleep Out Command (11h). Restriction -When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command because of the stabilization timing for the supply voltages and clock circuits.
Default
Status Power On Sequence S/W Reset H/W Reset Default Value Sleep in mode Sleep in mode Sleep in mode
Ver 1.6
109
2008-05
ST7713
10.1.12 SLPOUT (11h): Sleep Out
11H Inst / Para SLPOUT 1st Parameter D/CX 0 WRX
RDX 1
D17-8 -
SLPOUT (Sleep Out) D7 D6 D5 D4 0 0 0 1 No Parameter
D3 0
D2 0
D1 0
D0 1
(Code) (11h) -
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command turns off sleep mode. -In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started.
Sleep Out VDDI VDD Internal Oscillator AVDD VGL STOP 0V or VDD 0V 0V or VDD STOP 0V STOP 0V 0V STOP 0V 0V
Memory Contents Memory Contents
1.6V-3.0V 2.6V-3.0V Start
Description
VGH Internal counter IC Internal reset Gate Output Source Output VCOM Output
Start
Blanking display (over 1fram e display) * If DISPON 29h is set * Note: complete 1 frame display (ex: continue 2-falling edges of VS)
-This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In Command (10h). -When IC is in Sleep In mode, it is necessary to wait 120msec before sending next command because of Restriction the stabilization timing for the supply voltages and clock circuits. -When IC is in Sleep Out or Display On mode, it is necessary to wait 120msec before sending next command due to the download of default value of registers and the execution of self-diagnostic function.
Status Power On Sequence S/W Reset H/W Reset Default Value Sleep in mode Sleep in mode Sleep in mode
Default
Ver 1.6
110
2008-05
ST7713
10.1.13 PTLON (12h): Partial Display Mode On
12H Inst / Para PTLON st 1 Parameter D/CX 0 WRX
RDX 1
PTLON (12h): Partial Display Mode On D17-8 D7 D6 D5 D4 D3 D2 0 0 0 1 0 0 No Parameter
D1 1
D0 0
(Code) (12h) -
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command turns on Partial mode. The partial mode window is described by the Partial Area command Description (30h) -To leave Partial mode, the Normal Display Mode On command (13H) should be written.
Status Power On Sequence S/W Reset H/W Reset Default Value Normal Mode On Normal Mode On Normal Mode On
Default
10.1.14 NORON (13h): Normal Display Mode On
13H Inst / Para NORON st 1 Parameter D/CX 0 WRX
RDX 1
NORON (Normal Display Mode On) D17-8 D7 D6 D5 D4 D3 0 0 0 1 0 No Parameter
D2 0
D1 1
D0 1
(Code) (13h) -
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command returns the display to normal mode. Description -Normal display mode on means Partial mode off, Scroll mode Off. -Exit from NORON by the Partial mode On command (12h)
Status Power On Sequence S/W Reset H/W Reset Default Value Normal Mode On Normal Mode On Normal Mode On
Default
10.1.15 INVOFF (20h): Display Inversion Off
20H Inst / Para INVOFF st 1 Parameter D/CX 0 WRX
RDX 1
IVNOFF (Normal Display Mode Off) D17-8 D7 D6 D5 D4 D3 0 0 1 0 0 No Parameter
D2 0
D1 0
D0 0
(Code) (20h) -
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command is used to recover from display inversion mode.
(Example)
Top-Left (0,0)
Memory
Display
Description
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value Display Inversion off Display Inversion off Display Inversion off
Ver 1.6
111
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ST7713
10.1.16 INVON (21h): Display Inversion On
21H Inst / Para INVON st 1 Parameter D/CX 0 WRX
RDX 1
IVNOFF (Display Inversion On) D17-8 D7 D6 D5 D4 D3 0 0 1 0 0 No Parameter
D2 0
D1 0
D0 1
(Code) (21h) -
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command is used to enter into display inversion mode -To exit from Display Inversion On, the Display Inversion Off command (20h) should be written.
(Example)
Description
Top-Left (0,0)
Memory
Display
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value Display Inversion off Display Inversion off Display Inversion off
10.1.17 GAMSET (26h): Gamma Set
26H Inst / Para GAMSET
1st Parameter
D/CX 0
1
WRX

RDX 1 1
D17-8 -
D7 0 -
GAMSET (Gamma Set) D6 D5 D4 D3 0 1 0 0 GC3
D2 1
GC2
D1 1
GC1
D0 0
GC0
(Code) (26h)
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be selected. The curves are defined in section 9.17 The curve is selected by setting the appropriate bit in the parameter as described in the Table.
GC [7:0] Parameter GC0 GC1 GC2 GC3
Description
01h 02h 04h 08h
Curve Selected GS=1 GS=0 Gamma Curve 1 (G2.2) Gamma Curve 1 (G1.0) Gamma Curve 2 (G1.8) Gamma Curve 2 (G2.5) Gamma Curve 3 (G2.5) Gamma Curve 3 (G2.2) Gamma Curve 4 (G1.0) Gamma Curve 4 (G1.8)
Note: All other values are undefined. Status Power On Sequence S/W Reset H/W Reset Default Value 01h 01h 01h
Default
Ver 1.6
112
2008-05
ST7713
10.1.18 DISPOFF (28h): Display Off
28H Inst / Para DISPOFF st 1 Parameter D/CX 0 WRX
RDX 1
D17-8 -
DISPOFF (Display Off) D7 D6 D5 D4 0 0 1 0 No Parameter
D3 1
D2 0
D1 0
D0 0
(Code) (28h) -
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disables and blank page inserted. -Exit from this command by Display On (29h) -When IC is in Display On mode, it is necessary to wait 50msec before sending next command.
(Example)
Top-Left (0,0)
Memory
Display
Display OFF VDDI VDD 1.6V-3.0V 2.6V-3.0V VGH OP
Description
Gate Output Source Output VCOM Output Internal counter Internal Oscillator VGH VGL AVDD IC Internal reset 0V 0V Blanking display (over 1 frame display) *
STOP
Note1: Complete 1 frame display (ex: continue 2-falling edges of VS) Note2: Please use command 28h (display off) combined with command 10h (sleep in) to make module into display off status. Please check the application note of ST7713 when using display off function.
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value Display off Display off Display off
Ver 1.6
113
2008-05
ST7713
10.1.19 DISPON (29h): Display On
29H Inst / Para DISPON st 1 Parameter D/CX 0 WRX
RDX 1
D17-8 -
DISPON (Display On) D7 D6 D5 D4 0 0 1 0 No Parameter
D3 1
D2 0
D1 0
D0 1
(Code) (29h) -
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled.
(Example)
Top-Left (0,0)
Memory
Display
Display ON VDDI 1.6V-3.3V Blanking display (over 1 frame display) * STOP 0V 0V STOP Start
Memory Contents Memory Contents
Description
VDD Gate Output Source Output VCOM Output Internal counter Internal Oscillator VGH VGL AVDD IC Internal reset
2.5V-3.3V
* Note: complete 1 frame display (ex: continue 2-falling edges of VS)
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value Display off Display off Display off
Ver 1.6
114
2008-05
ST7713
10.1.20 CASET (2Ah): Column Address Set
2AH Inst / Para GAMSET
1st Parameter 2nd Parameter 3rd Parameter 4th Parameter
D/CX 0
1 1 1 1
WRX

RDX 1
1 1 1 1
D17-8 -
CASET(Colume Address Set)_ D7 D6 D5 D4 D3 0 0 1 0 0
XS15 XS7 XE15 XE7 XS14 XS6 XE14 XE6 XS13 XS5 XE13 XE5 XS12 XS4 XE12 XE4 XS11 XS3 XE11 XE3
D2 1
XS10 XS2 XE10 XE2
D1 1
XS9 XS1 XE9 XE1
D0 0
XS8 XS0 XE8 XE0
(Code) (2Ah)
NOTE: "-" Don't care, can be set to VDDI or DGND level
-The value of XS [15:0] and XE [15:0] are referred when RAMWR command comes. -Each value represents one column line in the Frame Memory. (Example)
XS[7:0] XE[7:0]
Description
XS [15:0] always must be equal to or less than XE [15:0] When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored. 1. 132x132 memory base (Parameter range: 0 XS [15:0] XE [15:0] 131 (0083h)): MV="0" (Parameter range: 0 XS [15:0] XE [15:0] 131 (0083h)): MV="1"
Status
Status
Default Value
Default
Ver 1.6
115
2008-05
ST7713
10.1.21 RASET (2Bh): Row Address Set
2BH Inst / Para RASET (2Bh)
1st Parameter 2nd Parameter 3rd Parameter 4th Parameter
D/CX 0
1 1 1 1
WRX

RDX 1
1 1 1 1
D17-8 -
D7 0
RASET (Row Address Set) D6 D5 D4 D3 0 1 0 1
YS14 YS6 YE14 YE6 YS13 YS5 YE13 YE5 YS12 YS4 YE12 YE4 YS11 YS3 YE11 YE3
D2 0
YS10 YS2 YE10 YE2
D1 1
YS9 YS1 YE9 YE1
D0 1
YS8 YS0 YE8 YE0
(Code) (2Bh)
YS15 YS7 YE15 YE7
NOTE: "-" Don't care, can be set to VDDI or DGND level
The value of YS [15:0] and YE [15:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory.
Example YS[7:0]
Description
YE[7:0]
YS [15:0] always must be equal to or less than YE [15:0] When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range will be ignored. 1. 132X132 memory base (Parameter range: 0 YS [15:0] YE [15:0] 131 (0083h)): MV="0" (Parameter range: 0 YS [15:0] YE [15:0] 131 (0083h)): MV="1"
status
Status
Default Value
Default
Ver 1.6
116
2008-05
ST7713
10.1.22 RAMWR (2Ch): Memory Write
2CH Inst / Para RAMWR 1st Parameter D/CX 0 1 1 1 WRX

Nth Parameter
RDX 1 1 1 1
D17-8 D17-8
RAMWR (Memory Write) D7 D6 D5 D4 0 0 1 0 D7 D6 D5 D4
D3 1 D3
D2 1 D2
D1 0 D1
D0 0 D0
(Code) (2Ch) -
D17-8
D7
D6
D5
D4
D3
D2
D1
D0
-
NOTE: "-" Don't care, can be set to VDDI or DGND level
-When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. -The Start Column/Start Row positions are different in accordance with MADCTL setting. (See section 9.12) -Sending any other command can stop Frame Write. Description In all color modes, there is no restriction on length of parameters. -1. 132x132 memory base 132x132x18-bit memory can be written on this command. Memory range: (0000h,0000h) -> (0083h,0083h)
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared
Ver 1.6
117
2008-05
ST7713
10.1.23 RAMHD (2Eh): Memory Read
2EH Inst / Para RAMHD
1st Parameter 2nd Parameter
D/CX 0
1 1 1 1
WRX
RDX 1

D17-8 D17-8
RAMHD (Memory Read) D7 D6 D5 D4 D3 0 0 1 0 1
D2 1
D1 1
D0 0
(Code) (2Eh)
(N+1)th Parameter
1 1 1 1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
-
-
D17-8
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command is used to transfer data from frame memory to MCU. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. -The Start Column/Start Row positions are different in accordance with MADCTL setting. (See section 9.12) -Then D[17:0] is read back from the frame memory and the column register and the row register incremented as section 9.10.2. Description -Frame Read can be cancelled by sending any other command. -The data color coding is fixed to 18-bit in reading function. Please see section 9.8 "Data color coding" for color coding (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data.
Note1: The Command 3Ah should be set to 66h when reading pixel data from frame memory.Please check the LUT in chapter 9.19 when using memory read function. Status Power On Sequence S/W Reset H/W Reset Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared
Default
Ver 1.6
118
2008-05
ST7713
10.1.25 PTLAR (30h): Partial Area
30H Inst / Para PTLAR
1st Parameter 2nd Parameter 3rd Parameter 4th Parameter
D/CX WRX 0
1 1 1 1

RDX D17-8 1 1 1 1 1 -
D7 0
PSL7 PEL7
PTLAR (Partial Area) D6 D5 D4 D3 0 1 1 0
PSL6 PEL6 PSL5 PEL5 PSL4 PEL4 PSL3 PEL3
D2 0
PSL2 PEL2
D1 0
PSL1 PEL1
D0 0
PSL0 PEL0
(Code) (30h)
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command defines the partial mode's display area. -There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter.
-If End Row > Start Row, when MADCTL ML='0'
Start Row PSL [7:0] Partial Display Area PEL [7:0] End Row Non-displaying Area Non-displaying Area
-If End Row > Start Row, when MADCTL ML='1'
End Row Non-displaying Area
Description
PEL [7:0] Partial Display Area PSL [7:0] Start Row Non-displaying Area
-If End Row < Start Row, when MADCTL ML='0'
End Row PEL [7:0] Non-displaying Area PSL [7:0] Start Row Partial Display Area Partial Display Area
-If End Row = Start Row then the Partial Area will be one row deep.
Status Default Value PEL [15:0] 0083h 0083h 0083h
Default
Power On Sequence S/W Reset H/W Reset
PSL [15:0] 0000h 0000h 0000h
Ver 1.6
119
2008-05
ST7713
10.1.26 SCRLAR (33h): Scroll Area
33H Inst / Para PTLAR
1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 5th Parameter 6th Parameter
D/CX WRX RDX D17-8 0 1 1 1 1 1 1 1

D7 0
TFA 7 VSA 7 BFA 7
SCRLAR (Scrolll Area) D6 D5 D4 D3 0 1 1 0
TFA 6 VSA 6 BFA 6 TFA 5 VSA 5 BFA 5 TFA 4 VSA 4 BFA 4 TFA 3 VSA 3 BFA 3
D2 0
TFA 2 VSA 2 BFA 2
D1 1
D0 1
(Code) (33h)
1 1 1 1 1 1
-
TFA 1 TFA 0 VSA 1 VSA 0 BFA 1 BFA 0
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command defines the Vertical Scrolling Area of the display. When MADCTL ML=0 st nd The 1 & 2 parameter TFA [7:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display). rd th The 3 & 4 parameter VSA [7:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the bottom most line of the Top Fixed Area. th th The 5 & 6 parameter BFA [7:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). TFA, VSA and BFA refer to the Frame Memory row address.
Top-Left (0,0)
Top Fixed Area TFA [7:0] Scroll Fixed Area VSFA [7:0] Bottom Fixed Area BFA [7:0] First line read from
When MADCTL ML=1 st nd The 1 & 2 parameter TFA [7:0] describes the Top Fixed Area (in No. of lines from Bottom Description of the Frame Memory and Display). rd th The 3 & 4 parameter VSA [7:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the top most line of the Top Fixed Area. th th The 5 & 6 parameter BFA [7:0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory and Display).
Top-Left (0,0)
Bottom Fixed Area BFA [7:0] Scroll Fixed Area VSFA [7:0] Top Fixed Area TFA [7:0] First line read from frame memory
See Section 9.10.4 for details of the Memory to Display Mapping. -The condition is 0(TFA+VSA+BFA) 132, otherwise Scrolling mode is undefined. -In Vertical Scroll Mode, MADCTL parameter MV should be set to `0'-this only affects the Frame Memory Write.
tatus Default Value VSA [15:0] 0083h 0083h 0083h
Default
Power On Sequence S/W Reset H/W Reset
TFA [15:0] 0000h 0000h 0000h
BFA [15:0] 0000h 0000h 0000h
Ver 1.6
120
2008-05
ST7713
1. To Enter Vertical Scroll Mode
Normal Mode SCRLAR (33h)
Display
Legend
Command
Parameter
1st & 2nd Parameter: TFA[7:0] 3rd & 4th Parameter VSA[7:0] 5th & 6th Parameter BFA[7:0] CASET (2Ah) 1st & 2nd Parameter XS[7:0] 3rd & 4th Parameter XE[7:0]
Action Mode Sequential transfer
Redefines the Frame memory Window that
the scroll data will be define
RASET (2
1st & 2nd Parameter YS[7:0]
Flow Chart
Only required for non-rolling scrolling
3rd & 4th Parameter YE[7:0] MADCTL (36h) Parameter: MY,MX,MV,ML,RGB RAMRW (2Ch) Scroll Image Data VSCSAD (37h)
1st & 2nd Parameter SS A[7:0]1
Optional - It may be necessary to redefine the Frame Memory Write Direction.
Scroll Mode
NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed.
Ver 1.6
121
2008-05
ST7713
Legend
2. Continuous Scroll
Command
Normal Mode CASET (2Ah) 1st 3
rd
Parameter
Display
&2nd Parameter XS[7:0] & 4 Parameter XE[7:0] RASET (2Bh)
th
Action Mode Sequential transfer
1st & 2nd Parameter YS[7:0] 3rd & 4th Parameter YE[7:0] RAMRW (2Ch) Only required for non-rolling scrolling Scroll Image Data VSCSAD (37h) 1st & 2nd Parameter SSA[7:0]1
3. To Exit Vertical Scroll Mode
Scroll Mode DISOFF (28h) NORON (13h) / PTLON (12h) Scroll Mode OFF RAMRW (2Ch) OptionTo prevent Tearing Effect Image Display
Image Data D1[17:0],D2[17:0]... Dn[17:0] DISON (29h)
NOTE: Scroll Mode can be exit by both the Normal Display Mode On (13h) and Partial Mode On (12h) commands.
Ver 1.6
122
2008-05
ST7713
10.1.27 TEOFF (34h): Tearing Effect Line OFF
34H Inst / Para TEOFF 1st Parameter D/CX 0 WRX
RDX 1
TEOFF (Tearing Effect Line OFF) D17-8 D7 D6 D5 D4 D3 0 0 1 1 0 No Parameter
D2 1
D1 0
D0 0
(Code) (34h) -
NOTE: "-" Don't care, can be set to VDDI or DGND level
Description -This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
Status Power On Sequence S/W Reset H/W Reset Default Value OFF OFF OFF
Default
10.1.28 TEON (35h): Tearing Effect Line ON
35H Inst / Para TEON 1st Parameter D/CX 0 1 WRX

RDX 1 1
D17-8 -
TEON (Tearing Effect Line ON) D7 D6 D5 D4 D3 0 0 1 1 0
0 0 0 0 0
D2 1
0
D1 0
0
D0 1
TELOM
(Code) (35h)
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command is used to turn ON the Tearing Effect output signal from the TE signal line. -This output is not affected by changing MADCTL bit ML. -The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. ("-"=Don't Care). When TELOM='0':
The Tearing Effect Output line consists of V-Blanking information only.
tvdl tvdh
Description
Vertical time scale When TELOM='1':
The Tearing Effect Output line consists of both V-Blanking and H-Blinking information.
tvdl tvdh
Vertical time scale
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value Tearing effect off & TELOM=0 Tearing effect off & TELOM=0 Tearing effect off & TELOM=0
Ver 1.6
123
2008-05
ST7713
10.1.29 MADCTL (36h): Memory Data Access Control
36H Inst / Para
MADCTL (Memory Data Access Control)
D/CX 0 1 WRX

MADCTL
1st Parameter
RDX 1 1
D17-8 -
D7 0
MY
D6 0
MX
D5 1
MV
D4 1
ML
D3 0
RGB
D2 1
-
D1 1
-
D0 0
-
(Code) (36h)
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command defines read/ write scanning direction of frame memory. -Bit Assignment
Bit MY MX MV ML NAME Row Address Order Column Address Order Row/Column Exchange Vertical Refresh Order DESCRIPTION These 3bits controls MCU to memory write/read direction. (See Section 9.12) LCD vertical refresh direction control `0' = LCD vertical refresh Top to Bottom `1' = LCD vertical refresh Bottom to Top Color selector switch control `0' =RGB color filter panel, `1' =BGR color filter panel)
RGB
RGB-BGR ORDER
ML: Vertical Refresh Order
Top-Left (0,0)
Memory
Sent First Sent 2nd Sent 3rd
Display
ML='0'
Sent Last
Description
Top-Left (0,0)
Memory
Sent Last
Display
ML='1'
Sent 3rd Sent 2nd Sent First
RGB: RGB-BGR Order RGB="0" Driver IC
RGB RGB SIG1 RG B RGB SIG2 RGB RGB SIG132 RGB RGB
SIG1
RGB="1" Driver IC
RG B R GB SIG2 RG R G BB SIG132
SIG1 RGB BGB R RG
SIG2 RGB B RGB B
SIG132 RGB B RGB B
SIG1
SIG2
SIG132 BGR BG BGR R
BGR BG BGR R
BGR B GR BGR R
LCD Panel
LCD Panel
Default
Status Power On Sequence S/W Reset H/W Reset
Default Value MY=0,MX=0,MV=0,ML=0,RGB=0 No Change MY=0,MX=0,MV=0,ML=0,RGB=0
Ver 1.6
124
2008-05
ST7713
10.1.30 VSCSAD (37h): Vertical Scroll Start Address of RAM
37H Inst / Para VSCSAD
1st Parameter 2nd Parameter
VSCSAD (Vertical Scroll Start Address of RAM)
D/CX 0 1 1 WRX

RDX 1 1 1
D17-8 -
D7 0
SSA7
D6 0
SSA6
D5 1
SSA5
D4 1
SSA4
D3 0
SSA3
D2 1
SSA2
D1 1
SSA1
D0 1
SSA0
(Code) (37h)
Note: "-" Don't care, can be set to VDDI or DGND level
-This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area and the scrolling mode. -The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below: -This command Start the scrolling. -Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h).
When MADCTL ML= `0'
Example: When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=130 and Vertical Scrolling Pointer SSA= '3'.
(Example)
Top-Left (0,0) Scan address
Memory
0 1 2 3 130 131 G1 G2 G3 G4 | | G131 G132
Display
Description
SSA[7:0] Scroll start address
When MADCTL ML = `1' Example: When Top Fixed Area= Bottom Fixed Area=00, Vertical Scrolling Area=130 and SSA= '3'
(Example)
Top-Left (0,0) Scan address
Memory
131 130 3 2 1 0 G1 G2 G3 G4 | | G131 G132
Display
SSA[7:0] Scroll start address
NOTE: -When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. -SSA refers to the Frame Memory scan address.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes No No Yes Default Value 0000h 0000h 0000h
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset
Default
Ver 1.6
125
2008-05
ST7713
10.1.31 IDMOFF (38h): Idle Mode Off
38H Inst / Para IDMOFF 1st Parameter D/CX 0 WRX
IDMOFF (Idle Mode Off) RDX 1 D17-8 D7 D6 D5 0 0 1 No Parameter D4 1 D3 1 D2 0 D1 0 D0 0 (Code) (38h) -
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command is used to recover from Idle mode on. -In the idle off mode, Description 1. LCD can display 4096, 65k or 262k colors. 2. Normal frame frequency is applied.
Status Power On Sequence S/W Reset H/W Reset Default Value Idle Mode Off Idle Mode Off Idle Mode Off
Default
10.1.32 IDMON (39h): Idle Mode On
39H Inst / Para IDMOFF 1st Parameter D/CX 0 WRX
RDX 1
D17-8 -
IDMON (Idle Mode On) D7 D6 D5 D4 0 0 1 1 No Parameter
D3 1
D2 0
D1 0
D0 1
(Code) (39h) -
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This command is used to enter into Idle mode on. -There will be no abnormal visible effect on the display mode change transition. -In the idle on mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38h) command
(Example)
Top-Left (0,0)
Mem ory
Display
Description
Color Black Blue Red Magenta Green Cyan Yellow White
R5 R4 R3 R2 R1 R0 0xxxxx 0xxxxx 1xxxxx 1xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx
G5 G4 G3 G2 G1 G0 0xxxxx 0xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx 1xxxxx 1xxxxx
B5 B4 B3 B4 B1 B0 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx
Ver 1.6
126
2008-05
ST7713
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes No No Yes Default Value Idle Mode Off Idle Mode Off Idle Mode Off
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset
Default
10.1.33 COLMOD (3Ah): Interface Pixel Format
3AH Inst / Para D/CX WRX COLMOD 0 1st Parameter 1 RDX 1 1 D17-8 COLMOD (3Ah): Interface Pixel Format D7 0
VIPF3
D6 0
VIPF2
D5 1
VIPF1
D4 1
VIPF0
D3 1
-
D2 0
IFPF2
D1 1
IFPF1
D0 0
IFPF0
(Code) (3Ah)
NOTE: "-" Don't care, can be set to VDDI or DGND level
This command is used to define the format of RGB picture data, which is to be transferred via the MCU interface and RGB interface. The formats are shown in the table:
IFPF[2:0] 011 101 110 111 3 5 6 7 MCU Interface Color Format 12-bit/pixel 16-bit/pixel 18-bit/pixel No used
Others are no define and invalid
VIFPF[2:0] 0101 0110 0111 1110 5 6 7 14 RGB Interface Color Format 16-bit/pixel (1-times data transfer) 18-bit/pixel (1-times data transfer) No used 18-bit/pixel (3-times data transfer)
Description
Others are no define and invalid
Note1: In 12-bit/Pixel, 16-bit/Pixel or 18-bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory. Note2: When RGB I/F the 12-bit/pixel don't care Note3: When VIPF[3:0]="1110",6-bit data width of 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information. Note4: The Command 3Ah should be set at 55h when writing 16-bit/pixel data into frame memory, but 3Ah should be re-set to 66h when reading pixel data from frame memory. Please check the LUT in chapter 9.19 when using memory read function. Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes No No Yes Default Value IFPF[2:0] VIPF[3:0] 0110(18-bit/Pixel) No Change 0110(18-bit/Pixel) 0110(18-bit/Pixel) No Change 0110(18-bit/Pixel)
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset
Default
Ver 1.6
127
2008-05
ST7713
10.1.34 RDID1 (DAh): Read ID1 Value
DAH Inst / Para RDID1
1st Parameter 2nd Parameter
RDID1 (Read ID1 Value) D/CX 0
1 1
WRX
RDX 1

D17-8 -
D7 1
ID17
D6 1
ID16
D5 0
ID15
D4 1
ID14
D3 1
ID13
D2 0
ID12
D1 1
ID11
D0 0
ID10
(Code) (DAh)
-
1 1
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This read byte returns 8-bit LCD module's manufacturer ID st -The 1 parameter is dummy data Description nd -The 2 parameter (ID17 to ID10): LCD module's manufacturer ID. nd NOTE: See command RDDID (04h), 2 parameter.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes No No Yes Default Value -
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset
Default
10.1.35 RDID2 (DBh): Read ID2 Value
DBH Inst / Para RDID2
1st Parameter 2nd Parameter
D/CX 0
1 1
WRX
RDX 1

D17-8 -
RDID2 (Read ID2 Value) D7 D6 D5 D4 D3 1 1 0 1 1
1 ID26 ID25 ID24 ID23
D2 0
ID22
D1 1
ID21
D0 1
ID20
(Code) (DBh)
-
1 1
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This read byte returns 8-bit LCD module/driver version ID st -The 1 parameter is dummy data nd -The 2 parameter (ID26 to ID20): LCD module/driver version ID -Parameter Range: ID=80h to FFh Description
ID26 to ID20 80h 81h 82h 83h
rd
Version
Changes
NOTE: See command RDDID (04h), 3 parameter.
Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes No No Yes Default Value 80h 80h 80h
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset
Default
Ver 1.6
128
2008-05
ST7713
10.1.36 RDID3 (DCh): Read ID3 Value
DCH Inst / Para RDID3
1st Parameter 2nd Parameter
RDID3 (Read ID2 Value) D/CX 0
1 1
WRX
RDX 1

D17-8 -
D7 1
ID37
D6 1
ID36
D5 0
ID35
D4 1
ID34
D3 1
ID33
D2 1
ID32
D1 0
ID31
D0 0
ID30
(Code) (DCh)
-
1 1
NOTE: "-" Don't care, can be set to VDDI or DGND level
-This read byte returns 8-bit LCD module/driver ID. st -The 1 parameter is dummy data Description -The 2nd parameter (ID37 to ID30): LCD module/driver ID.
NOTE: See command RDDID (04h), 4th parameter. Status Normal Mode On, Idle Mode Off, Sleep Out Availability Yes Yes No No Yes Default Value 00h 00h 00h
Register Availability
Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset
Default
10.2.1 RGBCTR (B0h): RGB signal control
B0H Inst / Para
RGBCTR (RGB signal control)
D/CX 0 1 WRX

RGBCTR
1st Parameter
RDX 1 1
D17-8 -
D7 1
0
D6 0
0
D5 1
DISSW
D4 1
ICM
D3 0
DP
D2 0
EP
D1 0
HSP
D0 0
VSP
(Code) (B0h)
NOTE: "-" Don't care
-Set the operation status on the RGB interface. The setting becomes effective as soon as the command is received.
-ICM: GRAM Write/Read frequency and data input select on the RGB interface
ICM 0 1
Write cycle PCLK SCL Write/ Read frequency and input data select Read cycle PCLK Internal oscillator Data input D[17:0] SDA
Description
Symbol DP EP HSP VSP DISSW
Name PCLK polarity set Enable polarity set Hsync polarity set Vsync polarity set Disable S/W
Clock polarity set for RGB Interface `1' = data fetched at the falling edge `0' = data fetched at the rising edge `1' = Low enable for RGB interface `0' = High enable for RGB interface `1' = High level sync clock `0' = Low level sync clock `1' = High level sync clock `0' = Low level sync clock `1' = Disable S/W control `0' = Enable S/W control
Status
Default
Power On Sequence S/W Reset H/W Reset
ICM 0d 0d 0d
Default Value DP/EP/HSP/VSP 0d/0d/0d/0d 0d/0d/0d/0d 0d/0d/0d/0d
Ver 1.6
129
2008-05
ST7713
10.2.2 FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors)
B1H Inst / Para FRMCTR1
1st Parameter 2nd Parameter 3rd Parameter NOTE: "-" Don't care
D/CX 0
1 1 1
WRX

RDX 1
1 1 1
D17-8 -
FRMCTR1 (Frame Rate Control) D7 D6 D5 D4 D3 D2 1 0 1 1 0 0
RTNA3 FPA3 BPA3 RTNA2 FPA2 BPA2
D1 0
RTNA1 FPA1 BPA1
D0 1
RTNA0 FPA0 BPA0
(Code) (B1h)
-
Description
-Set the frame frequency of the full colors normal mode. - Frame rate=fosc/((RTNA + 18) x (LINE + FPA + BPA))
- 1 < FPA(front porch) + BPA(back porch)<=22
Status Power On Sequence S/W Reset H/W Reset Default Value 06h/03h/02h 06h/03h/02h 06h/03h/02h
Default
10.2.3 FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors)
B2H Inst / Para FRMCTR2
1st Parameter 2nd Parameter 3rd Parameter NOTE: "-" Don't care
D/CX 0
1 1 1
WRX

RDX 1
1 1 1
D17-8 -
FRMCTR2 (Frame Rate Control) D7 D6 D5 D4 D3 D2 1 0 1 1 0 0
RTNB3 FPB3 BPB3 RTNB2 FPB2 BPB2
D1 1
RTNB1 FPB1 BPB1
D0 0
RTNB0 FPB0 BPB0
(Code) (B2h)
-
Description
-Set the frame frequency of the Idle mode. - Frame rate=fosc/((RTNB + 18) x (LINE + FPB + BPB))
- 1 < FPB(front porch) + BPB(back porch)<=22
Status Power On Sequence S/W Reset H/W Reset Default Value 06h/03h/02h 06h/03h/02h 06h/03h/02h
Default
10.2.4 FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors)
B3H Inst / Para FRMCTR3
1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 5th Parameter 6th Parameter NOTE: "-" Don't care
D/CX 0
1 1 1 1 1 1
WRX

RDX 1
1 1 1 1 1 1
D17-8 -
FRMCTR3 (Frame Rate Control) D7 D6 D5 D4 D3 D2 1 0 1 1 0 0
RTNC3 FPC3 BPC3 RTND3 FPD3 BPD3 RTNC2 FPC2 BPC2 RTND2 FPD2 BPD2
D1 1
RTNC1 FPC1 BPC1 RTND1 FPD1 BPD1
D0 1
RTNC0 FPC0 BPC0 RTND0 FPD0 BPD0
(Code) (B3h)
-
-
-
-Set the frame frequency of the Partial mode/ full colors. - 1st parameter to 3rd parameter are used in line inversion mode. Description - 4th parameter to 6th prameter are used in frame inversion mode. - Frame rate=fosc/((RTNC + 18) x (LINE + FPC + BPC))
- 1 < FPC(front porch) + BPC(back porch)<=22
Default
Status Power On Sequence S/W Reset H/W Reset Default Value
06h/03h/02h 06h/03h/02h 06h/03h/02h
Ver 1.6
130
2008-05
ST7713
10.2.5 INVCTR (B4h): Display Inversion Control
B4H Inst / Para INVCTR
1st Parameter NOTE: "-" Don't care
D/CX 0
1
WRX

RDX 1
1
INVCTR (Display Inversion Control) D17-8 D7 D6 D5 D4 D3 D2 1 0 1 1 0 1 0 0 0 0 0 NLA
D1 0
NLB
D0 0
NLC
(Code) (B4h)
02h
-Display Inversion mode control -NLA: Inversion setting in full colors normal mode (Normal mode on)
NLA 0 1 Inversion setting in full Colors normal mode Line Inversion Frame Inversion Inversion setting in Idle mode Line Inversion Frame Inversion Inversion setting in full Colors partial mode Line Inversion Frame Inversion
Status NLA 0d 0d 0d NLB 1d 1d 1d Default Value NLC 0d 0d 0d B4h 02h 02h 02h
-NLB: Inversion setting in Idle mode (Idle mode on)
Description
NLB 0 1 NLC 0 1
-NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off)
Default
Power On Sequence S/W Reset H/W Reset
10.2.6 RGBBPCTR (B5h): RGB Interface Blanking Porch setting
B5H Inst / Para RGBBPCTR
1st Parameter 2nd Parameter 3rd Parameter 4th Parameter NOTE: "-" Don't care
D/CX 0
1 1 1 1
WRX

RDX 1
1 1 1 1
RGBPSET (RGB Interface Blanking Porch setting) D17-8 D7 D6 D5 D4 D3 D2 -
D1 0
VBP1 HBP1
D0 1
VBP0 HBP8 HBP0
(Code) (B5h)
-
1
VBP7 HBP7
0
VBP6 HBP6
1
VBP5 HBP5
1
VBP4 HBP4
0
VBP3 HBP3
1
VBP2 HBP2
Description
-Set the blanking porch in the RGB interface -VBPVertical back porch -HBPHorizontal back porch
Ver 1.6
131
2008-05
ST7713
10.2.7 DISSET5 (B6h): Display Function set 5
B6H Inst / Para DISSET5
1st Parameter 2nd Parameter NOTE: "-" Don't care
DISSET (Display Function set 5)
D/CX 0
1 1
WRX

RDX 1
1 1
D17-8 -
D7 1 0 0
D6 0 0 0
D5 1 NO1 0
D4 1 NO0 0
D3 0 SDT1 PTG1
D2 1 SDT0 PTG0
D1 1 EQ1 PT1
D0 0 EQ0 PT0
(Code) (B6h)
16h 02h
-1st parameter: Set output waveform relation. -NO[1:0]: Set the amount of non-overlap of the gate output
NO[1:0]
00 01 10 11 0 1 2 3 Amount of non-overlap of the gate output Refer the Internal oscillator Refer the PCLK 1 clock cycle 4 clock cycle 4 clock cycle 16 clock cycle 6 clock cycle 24 clock cycle 8 clock cycle 32 clock cycle
-SDT[1:0]: Set delay amount from gate signal falling edge of the source output.
SDT[1:0]
00 01 10 11 0 1 2 3 Amount of non-overlap of the gate output Refer the Internal oscillator Refer the PCLK 1 clock cycle 4 clock cycle 4 clock cycle 16 clock cycle 6 clock cycle 24 clock cycle 8 clock cycle 32 clock cycle
-EQ[1:0]: Set the Equalizing period
EQ[1:0]
00 01 10 11 0 1 2 3 Amount of non-overlap of the gate output Refer the Internal oscillator Refer the PCLK No EQ No EQ 2 clock cycle 4 clock cycle 4 clock cycle 16 clock cycle 6 clock cycle 24 clock cycle
Description
Gn Gn+1 Sn VCOM
Delay time for
Gate Non-overlap period
source output
EQ period
-2nd parameter: Set the output waveform in non-display area. -PTG[1:0]: Determine gate output in a non-display area in the partial mode
PTG[1:0]
00 01 10 11 0 1 2 3 Gate output in a non-display area Normal scan Fix on VGL Fix on VGL Fix on VGL
-PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode
PT[1:0]
00 01 10 11 0 1 2 3 Source output on non-display area Positive Negative V63 V0 V0 V63 AGND AGND Hi-z Hi-z VCOM output on non-display area Positive Negative VCOML VCOMH VCOML VCOMH AGND AGND AGND AGND
Ver 1.6
132
2008-05
ST7713
10.2.8 PWCTR1 (C0h): Power Control 1
C0H Inst / Para PWCTR1
1st Parameter 2nd Parameter NOTE: "-" Don't care
D/CX 0
1 1
WRX

RDX 1
1 1
D17-8 -
D7 1
0 0
PWCTR1 (Power Control 1) D6 D5 D4 D3 1 0 0 0
0 0 0 0 VRH4 0 VRH3 0
D2 0
VRH2 VC2
D1 0
VRH1 VC1
D0 0
VRH0 VC0
(Code) (C0h)
-Set the GVDD and VCI1 voltage
VRH[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 VC[2:0] 000 001 010 011 100 101 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GVDD 5.00 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 3.95 3.90 3.85 3.80 3.75 3.70 3.65 3.60 3.55 3.50 3.45 3.40 3.35 3.25 3.00 VCI1 2.75 2.70 2.65 2.60 2.55 2.50
Description
0 1 2 3 4 5
Ver 1.6
133
2008-05
ST7713
10.2.9 PWCTR2 (C1h): Power Control 2
C1H Inst / Para PWCTR2
1st Parameter
D/CX 0
1
WRX

RDX 1
1
D17-8 -
D7 1
0
PWCTR2 (Power Control 2) D6 D5 D4 D3 1 0 0 0
0 0 0 0
D2 0
BT2
D1 0
BT1
D0 1
BT0
(Code) (C1h)
NOTE: "-" Don't care
-Set the AVDD, VCL, VGH and VGL supply power level
BT[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7
2xVDD 2xVDD 2xVDD 2xVDD 2xVDD 2xVDD 2xVDD 2xVDD
Description
AVDD 5.49 5.49 5.49 5.49 5.49 5.49 5.49 5.49
VCL
-1xVDD -1xVDD -1xVDD -1xVDD -1xVDD -1xVDD -1xVDD -1xVDD
-2.74 -2.74 -2.74 -2.74 -2.74 -2.74 -2.74 -2.74
4*VCI1 4* VCI1 5* VCI1 5* VCI1 5* VCI1 6* VCI1 6* VCI1 6* VCI1
VGHH 9.80 9.80 12.25 12.25 12.25 14.70 14.70 14.70
-3* VCI1 -4* VCI1 -3* VCI1 -4* VCI1 -5* VCI1 -3* VCI1 -4* VCI1 -5* VCI1
VGLL -7.35 -9.80 -7.35 -9.80 -12.25 -7.35 -9.80 -12.25
Note: When VCI1=2.5V, VDD=2.8V,Set-up cycle 1 effective=98%, Set-up cycle 2 effective=98%,
10.2.10 PWCTR3 (C2h): Power Control 3 (in Normal mode/ Full colors)
C2H Inst / Para PWCTR3
1st Parameter 2nd Parameter NOTE: "-" Don't care
D/CX 0
1 1
WRX

RDX 1
1 1
D17-8 -
PWCTR3 (Power Control 3) D7 D6 D5 D4 D3 1 1 0 0 0
0 0 0 0 0 0 0 0 0 0
D2 0
APA2 DCA2
D1 1
APA1 DCA1
D0 0
APA0 DCA0
(Code) (C2h)
-Set the amount of current in Operational amplifier in normal mode/full colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
AP[2:0] 000 001 010 011 100 101 110 111 DC[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7
Amount of Current in Operational Amplifier Operation of the operational amplifier stops Small Medium Low Medium Medium High Large Reserved Reserved
Description
-Set the Booster circuit Step-up cycle in Normal mode/ full colors.
0 1 2 3 4 5 6 7
Step-up cycle in Booster circuit 1 BCLK / 1 BCLK / 1 BCLK / 1 BCLK / 2 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 4 Step-up cycle in Booster circuit 2,3 BCLK / 1 BCLK / 2 BCLK / 4 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 8 BCLK / 16
Note: BCLK is Clock frequency for Booster circuit
Ver 1.6
134
2008-05
ST7713
10.2.11 PWCTR4 (C3h): Power Control 4 (in Idle mode/ 8-colors)
C3H Inst / Para PWCTR4
1st Parameter 2nd Parameter NOTE: "-" Don't care
D/CX 0
1 1
WRX

RDX 1
1 1
D17-8 -
PWCTR4 (Power Control 4) D7 D6 D5 D4 D3 1 1 0 0 0
0 0 0 0 0 0 0 0 0 0
D2 0
APB2 DCB2
D1 1
APB1 DCB1
D0 1
APB0 DCB0
(Code) (C3h)
-Set the amount of current in Operational amplifier in Idle mode/8 colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
AP[2:0] 000 001 010 011 100 101 110 111 DC[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7
Amount of Current in Operational Amplifier Operation of the operational amplifier stops Small Medium Low Medium Medium High Large Reserved Reserved
Description
-Set the Booster circuit Step-up cycle in Idle mode/8 colors.
0 1 2 3 4 5 6 7
Step-up cycle in Booster circuit 1 BCLK / 1 BCLK / 1 BCLK / 1 BCLK / 2 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 4 Step-up cycle in Booster circuit 2,3 BCLK / 1 BCLK / 2 BCLK / 4 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 8 BCLK / 16
Note: BCLK is Clock frequency for Booster circuit
Ver 1.6
135
2008-05
ST7713
10.2.12 PWCTR5 (C4h): Power Control 5 (in Partial mode/ full-colors)
C4H Inst / Para PWCTR5
1st Parameter 2nd Parameter NOTE: "-" Don't care
D/CX 0
1 1
WRX

RDX 1
1 1
D17-8 -
PWCTR5 (Power Control 5) D7 D6 D5 D4 D3 1 1 0 0 0
0 0 0 0 0 0 0 0 0 0
D2 1
APC2 DCC2
D1 0
APC1 DCC1
D0 0
APC0 DCC0
(Code) (C4h)
-Set the amount of current in Operational amplifier in Partial mode/ full-colors. -Adjust the amount of fixed current from the fixed current source in the operational amplifier for the source driver.
AP[2:0] 000 001 010 011 100 101 110 111 DC[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7
Amount of Current in Operational Amplifier Operation of the operational amplifier stops Small Medium Low Medium Medium High Large Reserved Reserved
Description
-Set the Booster circuit Step-up cycle in Partial mode/ full-colors.
0 1 2 3 4 5 6 7
Step-up cycle in Booster circuit 1 BCLK / 1 BCLK / 1 BCLK / 1 BCLK / 2 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 4 Step-up cycle in Booster circuit 2,3 BCLK / 1 BCLK / 2 BCLK / 4 BCLK / 2 BCLK / 4 BCLK / 4 BCLK / 8 BCLK / 16
Note: BCLK is Clock frequency for Booster circuit
Ver 1.6
136
2008-05
ST7713
10.2.13 VMCTR1 (C5h): VCOM Control 1
C5H Inst / Para VMCTR1
1st Parameter 2nd Parameter NOTE: "-" Don't care
D/CX 0
1 1
WRX

RDX 1
1 1
D17-8 -
D7 1
-
VMCTR1 (VCOM Control 1) D6 D5 D4 D3 1 0 0 0
VMH6 VML6
D2 1
D1 0
D0 1
(Code) (C5h)
VMH5 VMH 4 VMH 3 VMH 2 VMH 1 VMH 0 VML5 VML4 VML3 VML2 VML1 VML0
-Set VCOMH Voltage
VMH[6:0] 0000000 0 0000001 1 0000010 2 0000011 3 0000100 4 0000101 5 0000110 6 0000111 7 0001000 8 0001001 9 0001010 10 0001011 11 0001100 12 0001101 13 0001110 14 0001111 15 0010000 16 0010001 17 0010010 18 0010011 19 0010100 20 0010101 21 0010110 22 0010111 23 0011000 24 0011001 25 0011010 26 VML[6:0] 0000000 0 0000001 1 0000010 2 0000011 3 0000100 4 0000101 5 0000110 6 0000111 7 0001000 8 0001001 9 0001010 10 0001011 11 0001100 12 0001101 13 0001110 14 0001111 15 0010000 16 0010001 17 0010010 18 0010011 19 0010100 20 0010101 21 0010110 22 0010111 23 0011000 24 0011001 25 0011010 26 VCOMH
Description
2.500 2.525 2.550 2.575 2.600 2.625 2.650 2.675 2.700 2.725 2.750 2.775 2.800 2.825 2.850 2.875 2.900 2.925 2.950 2.975 3.000 3.025 3.050 3.075 3.100 3.125 3.150
VCOML
VMH[6:0] 0011011 0011100 0011101 0011110 0011111 0100000
VCOMH 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
0100001
0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101 VML[6:0] 0011011 0011100 0011101 0011110 0011111 0100000
3.175 3.200 3.225 3.250 3.275 3.300 3.325 3.350 3.375 3.400 3.425 3.450 3.475 3.500 3.525 3.550 3.575 3.600 3.625 3.650 3.675 3.700 3.725 3.750 3.775 3.800 3.825
VCOML
VMH[6:0] 0110110 54 0110111 55 0111000 56 0111001 57 0111010 58 0111011 59 0111100 60 0111101 61 0111110 62 0111111 63 1000000 64 1000001 65 1000010 66 1000011 67 1000100 68 1000101 69 1000110 70 1000111 71 1001000 72 1001001 73 1001010 74 1001011 75 1001100 76 1001101 77 1001110 78 1001111 79 1010000 80 VML[6:0] 0110110 54 0110111 55 0111000 56 0111001 57 0111010 58 0111011 59 0111100 60 0111101 61 0111110 62 0111111 63 1000000 64 1000001 65 1000010 66 1000011 67 1000100 68 1000101 69 1000110 70 1000111 71 1001000 72 1001001 73 1001010 74 1001011 75 1001100 76 1001101 77 1001110 78 1001111 79 1010000 80
VCOMH
3.850 3.875 3.900 3.925 3.950 3.975 4.000 4.025 4.050 4.075 4.100 4.125 4.150 4.175 4.200 4.225 4.250 4.275 4.300 4.325 4.350 4.375 4.400 4.425 4.450 4.475 4.500
VCOML
VMH[6:0] 1010001 81 1010010 82 1010011 83 1010100 84 1010101 85 1010110 86 1010111 87 1011000 88 1011001 89 1011010 90 1011011 91 1011100 92 1011101 93 1011110 94 1011111 95 1100000 96 1100001 97 1100010 98 1100011 99 1100100 100 1100101 101 | 1111111 127
VCOMH
4.525 4.550 4.575 4.600 4.625 4.650 4.675 4.700 4.725 4.750 4.775 4.800 4.825 4.850 4.875 4.900 4.925 4.950 4.975 5.000 Not Permitted
-Set VCOML Voltage
-2.500 -2.475 -2.450 -2.425 -2.400 -2.375 -2.350 -2.325 -2.300 -2.275 -2.250 -2.225 -2.200 -2.175 -2.150 -2.125 -2.100 -2.075 -2.050 -2.025 -2.000 -1.975 -1.950 -1.925 -1.900 -1.875
-1.850 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
0100001
0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 0101110 0101111 0110000 0110001 0110010 0110011 0110100 0110101
-1.825 -1.800 -1.775 -1.750 -1.725 -1.700 -1.675 -1.650 -1.625 -1.600 -1.575 -1.550 -1.525 -1.500 -1.475 -1.450 -1.425 -1.400 -1.375 -1.350 -1.325 -1.300 -1.275 -1.250 -1.225 -1.200 -1.175
-1.150 -1.125 -1.100 -1.075 -1.050 -1.025 -1.000 -0.975 -0.950 -0.925 -0.900 -0.875 -0.850 -0.825 -0.800 -0.775 -0.750 -0.725 -0.700 -0.675 -0.650 -0.625 -0.600 -0.575 -0.550 -0.525 -0.500
VML[6:0] 1010001 81 1010010 82 1010011 83 1010100 84 1010101 85 1010110 86 1010111 87 1011000 88 1011001 89 1011010 90 1011011 91 1011100 92 1011101 93 1011110 94 1011111 95 1100000 96 1100001 97 1100010 98 1100011 99 1100100 100 1100101 101 | 1111111 127
VCOML
-0.475 -0.450 -0.425 -0.400 -0.375 -0.350 -0.325 -0.300 -0.275 -0.250 -0.225 -0.200 -0.175 -0.150 -0.125 -0.100 -0.075 -0.050 -0.025
0.000
Not Permitted
Ver 1.6
137
2008-05
ST7713
10.2.14 VMOFCTR (C7h): VCOM Offset Control
C7H Inst / Para VMOFCTR
1st Parameter
D/CX 0
1
WRX

RDX 1
1
D17-8 -
VMOFCTR (VCOM Offset Control) D7 D6 D5 D4 D3 1 1 0 0 0
-
D2 1
VMF2
D1 1
VMF1
D0 1
VMF0
(Code) (C7h)
VMF6
-
-
VMF3
NOTE: "-" Don't care, can be set to VDDI or DGND level
-Set VCOM Voltage level for reduce the flicker issue
VMF[6] 0 0 0 0 0 0 1 1 1 1 1 1 VMF[3:0] 0000 0001 0010 1110 1111 0000 0001 0010 1110 1111 VCOMH Output Level "VMH"-16d "VMH"-15d "VMH"-14d | "VMH"-2d "VMH"-1d "VMH" "VMH"+1d "VMH"+2d | "VMH"+14d "VMH"+15d VCOML Output Level "VML"-16d "VML"-15d "VML"-14d | "VML"-2d "VML"-1d "VML" "VML"+1d "VML"+2d | "VML"+14d "VML"+15d
Description
- 1d=25mV, 2d=50mV 3d=75mv.... - 2.5V <= VMH nd <= 5.0V; -2. 5V <= VML nd<= 0V (n=0~15,16) - VMF[6] & VMF[3:0] are stored in NV memory to contrast.
Ver 1.6
138
2008-05
ST7713
10.2.15 WRID2 (D1h): Write ID2 Value
D1H Inst / Para WRID2
1st Parameter NOTE: "-" Don't care
D/CX 0
1
WRX

RDX 1
1
D17-8 -
D7 1
-
WRID2 (Write ID2 Value) D6 D5 D4 D3 1 0 1 0
ID26 ID25 ID24 ID23
D2 0
ID22
D1 0
ID21
D0 1
ID20
(Code) (D1h)
-
Description
-Write 7-bit data of LCD module version to save it to NV memory. -The parameter ID2[6:0] is LCD Module version ID.
Refer to Applcation Note
10.2.16 WRID3 (D2h): Write ID3 Value
D2H Inst / Para WRID3
1st Parameter NOTE: "-" Don't care
D/CX 0
1
WRX

RDX 1
1
D17-8 -
D7 1
ID37
WRID3 (Write ID3 Value) D6 D5 D4 D3 1 0 1 0
ID36 ID35 ID34 ID33
D2 0
ID32
D1 1
ID31
D0 0
ID30
(Code) (D2h)
-
Description
-Write 8-bit data of project code module to save it to NV memory. -The parameter ID3[7:0] is product project ID.
Refer to Applcation Note
10.2.17 RDID4 (D3h): Read the ID4 value
D3H Inst / Para RDID4
1st Parameter 2nd Parameter 3rd Parameter 4th Parameter 5th Parameter NOTE: "-" Don't care
D/CX WRX RDX 0 1
1 1 1 1 1 1 1 1 1 1

D17-8 -
RDID4 (Read the ID4 value) D7 D6 D5 D4 D3 1 1 0 1 0
ID417 ID427 ID437 ID447 ID416 ID426 ID436 ID446 ID415 ID425 ID435 ID445 ID414 ID424 ID434 ID444 ID413 ID423 ID433 ID443
D2 0
ID412 ID422 ID432 ID442
D1 1
ID411 ID421 ID431 ID441
D0 1
ID410 ID420 ID430 ID440
(Code) (D3h)
-
-Read the Driver IC information from mask value. -The 1st parameter is dummy data. Description -The 2nd parameter ID41[7:0]="03h" is Driver IC ID code. -The 3rd parameter ID42[7:0] is Driver IC Part number ID. (The code be define by Driver IC Vender) -The 4th & 5th parameter ID43[7:0] & ID44[7:0] are Driver IC version ID.
Status ID41[7:0] 03h 03h 03h Default Value ID42[7:0] ID43[7:0] 20h 01h 20h 01h 20h 01h ID44[7:0] 00h 00h 00h
Default
Power On Sequence S/W Reset H/W Reset
Ver 1.6
139
2008-05
ST7713
10.2.18 NVFCTR1 (D9h): NV Memory Function Controller 1
D9H Inst / Para NVFCTR1 1st Parameter
NOTE: "-" Don't care
D/CX 0 1
WRX
1
RDX 1
NVFCTR1 (NV Memory Function Controller 1) D17-8 D7 D6 D5 D4 D3 D2 1 1 0 1 1 0 EXTC -
D1 0 -
D0 1 RDY
(Code) (D9h) -
Description OTP Controller flag
Refer to Applcation Note
10.2.19 NVFCTR2 (DEh): NV Memory Function Controller 2
DEH Inst / Para NVFCTR1 st 1 Parameter nd 2 Parameter rd 3 Parameter
NOTE: "-" Don't care
D/CX 0 1 1 1
WRX

RDX 1 1 1 1
NVFCTR1 (NV Memory Function Controller 2) D17-8 D7 D6 D5 D4 D3 D2 1 1 0 1 1 1 1 0 1 0 1 0 0 0 0 0 1 1 1 0 1 0 0 1
D1 1 1 1 0
D0 0 0 1 1
(Code) (DEh) AA 0F A5
Description
OTP Read Command Refer to Applcation Note
10.2.20 NVFCTR3 (DFh): NV Memory Function Controller 3
DFH Inst / Para NVFCTR1 st 1 Parameter nd 2 Parameter rd 3 Parameter
NOTE: "-" Don't care
D/CX 0 1 1 1
WRX

RDX 1 1 1 1
NVFCTR1 (NV Memory Function Controller 3 D17-8 D7 D6 D5 D4 D3 D2 1 1 0 1 1 1 0 1 0 1 0 1 1 1 1 1 0 0 0 1 0 1 1 0
D1 1 0 0 1
D0 1 1 0 0
(Code) (DFh) 55 F0 5A
Description OTP Write Command
Refer to Applcation Note
Ver 1.6
140
2008-05
ST7713
10.2.21 GMCTRP1 (E0h): Gamma (`+'polarity) Correction Characteristics Setting
E0H Inst / Para GMCTRP1 1 Parameter nd 2 Parameter rd 3 Parameter th 4 Parameter th 5 Parameter th 6 Parameter th 7 Parameter th 8 Parameter th 9 Parameter th 10 Parameter th 11 Parameter th 12 Parameter th 13 Parameter
NOTE: "-" Don't care
st
D/CX 0 1 1 1 1 1 1 1 1 1 1 1 1 1
GMCTRP0 (Gamma `+'polarity Correction Characteristics Setting) WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0

(Code) (E0h)
1 1 1 1 1 1 1 1 1 1 1 1 1 1
-
1 -
1 -
1 -
0
0
0
0
0
RFP3 RFP2 RFP1 RFP0 PKP04 PKP03 PKP02 PKP01 PKP00 PKP14 PKP13 PKP12 PKP11 PKP10 PKP24 PKP23 PKP22 PKP21 PKP20 PKP34 PKP33 PKP32 PKP31 PKP30 PKP44 PKP43 PKP42 PKP41 PKP40 PKP53 PKP52 PKP51 PKP50 PKP63 PKP62 PKP61 PKP60 PKP73 PKP72 PKP71 PKP70 PKP83 PKP82 PKP81 PKP80 RFP14 RFP13 RFP12 RFP11 RFP10 OSP14 OSP13 OSP12OSP11 OSP10 OSP3 OSP2 OSP1 OSP0
Negative Polarity RFP[3:0] PKP0[4:0] PKP1[4:0] PKP2[4:0] PKP3[4:0] PKP4[4:0] PKP5[3:0] PKP6[3:0] PKP7[3:0] PKP8[3:0] RFP1[4:0] OSP1[4:0] OSP[3:0]
Set-up Contents The voltage of V0 grayscale is selected by the variable resistor The voltage of V3 grayscale is selected by the 32 to 1 selector The voltage of V6 grayscale is selected by the 32 to 1 selector The voltage of V11 grayscale is selected by the 32 to 1 selector The voltage of V20 grayscale is selected by the 32 to 1 selector The voltage of V31 grayscale is selected by the 32 to 1 selector The voltage of V43 grayscale is selected by the 16 to 1 selector The voltage of V52 grayscale is selected by the 16 to 1 selector The voltage of V57 grayscale is selected by the 16 to 1 selector The voltage of V60 grayscale is selected by the 16 to 1 selector The voltage of V1 grayscale is selected by the variable resistor The voltage of V62 grayscale is selected by the variable resistor The voltage of V63 grayscale is selected by the variable resistor
Description
Ver 1.6
141
2008-05
ST7713
10.2.22 GMCTRN1 (E1h): Gamma `-'polarity Correction Characteristics Setting
E1H Inst / Para GMCTRP1 1 Parameter nd 2 Parameter rd 3 Parameter th 4 Parameter th 5 Parameter th 6 Parameter th 7 Parameter th 8 Parameter th 9 Parameter th 10 Parameter th 11 Parameter th 12 Parameter th 13 Parameter
NOTE: "-" Don't care
st
D/CX 0 1 1 1 1 1 1 1 1 1 1 1 1 1
GMCTRP0 (Gamma `+'polarity Correction Characteristics Setting) WRX RDX D17-8 D7 D6 D5 D4 D3 D2 D1 D0

(Code) (E1h)
1 1 1 1 1 1 1 1 1 1 1 1 1 1
-
1 -
1 -
1 -
0 PKN04 PKN14 PKN24 PKN34 PKN44 RFN14 OSN14 -
0 RFN3 PKN03 PKN13 PKN23 PKN33 PKN43 PKN53 PKN63 PKN73 PKN83 RFN13 OSN13 OSN3
0 RFN2 PKN02 PKN12 PKN22 PKN32 PKN42 PKN52 PKN62 PKN72 PKN82 RFN12 OSN12 OSN2
0 RFN1 PKN01 PKN11 PKN21 PKN31 PKN41 PKN51 PKN61 PKN71 PKN81 RFN11 OSN11 OSN1
1 RFN0 PKN00 PKN10 PKN20 PKN30 PKN40 PKN50 PKN60 PKN70 PKN80 RFN10 OSN10 OSN0
Negative Polarity RFN[3:0] PKN0[4:0] PKN1[4:0] PKN2[4:0] PKN3[4:0] PKN4[4:0] PKN5[3:0] PKN6[3:0] PKN7[3:0] PKN8[3:0] RFN1[4:0] OSN1[4:0] OSN[3:0]
Set-up Contents The voltage of V63 grayscale is selected by the variable resistor The voltage of V60 grayscale is selected by the 32 to 1 selector The voltage of V57 grayscale is selected by the 32 to 1 selector The voltage of V52 grayscale is selected by the 32 to 1 selector The voltage of V43 grayscale is selected by the 32 to 1 selector The voltage of V31 grayscale is selected by the 32 to 1 selector The voltage of V20 grayscale is selected by the 16 to 1 selector The voltage of V11 grayscale is selected by the 16 to 1 selector The voltage of V6 grayscale is selected by the 16 to 1 selector The voltage of V3 grayscale is selected by the 16 to 1 selector The voltage of V62 grayscale is selected by the variable resistor The voltage of V1 grayscale is selected by the variable resistor The voltage of V0 grayscale is selected by the variable resistor
Description
Ver 1.6
142
2008-05
ST7713
10.2.23 DCTRM1 (F5h): Driver Vender Control 1
F5H Inst / Para DCTRM1 1st Parameter D/CX 0 1 WRX

RDX 1
1
D17-8 -
D7 1 B7
Driver Vender Control 1 D6 D5 D4 D3 1 1 1 0 B6 B5 B4 B3
D2 1 B2
D1 0 B1
D0 1 B0
(Code) (F5h) -
Description Driver Vender Control Command for optimization
Refer to Applcation Note for the parameter setting(B7~B0)
10.2.24 DCTRM2 (F6h): Driver Vender Control 2
F6H Inst / Para DCTRM2 1st Parameter D/CX 0 1 WRX

RDX 1 1
D17-8 -
D7 1 B7
Driver Vender Control 2 D6 D5 D4 D3 1 1 1 0 B6 B5 B4 B3
D2 1 B2
D1 1 B1
D0 0 B0
(Code) (F6h) -
Description Driver Vender Control Command for optimization
Refer to Applcation Note for the parameter setting(B7~B0)
Ver 1.6
143
2008-05
ST7713
11. Power structure 11.1. Driver IC Operating voltages Specification
VGH (9.4V ~ 16.1V)
AVDD VDD=(2.5V~3.3V)
Charge Pump Reference Voltage Internal Reference Voltage
AVDD (4.95V ~ 6V) GVDD (3.0V ~ 5.0V) VCOMH (2.5V ~ 5.0V)
AGND=0V VCOML (-2.5V ~ 0.0V) VCL (-2.5V ~ -2.9V)
VGL (-13.4V ~ -7.05V)
Fig. 11.1.1 Power Booster Level
Remark 1. AVDD supply to all power source (exclude VGH, VGL) 2. Source output range: 0.1V ~ AVDD-0.1V 3. Linear Range: 0.2V ~ AVDD-0.2V (For all output voltage, but exclude VGH, VGL) 4. Above operating voltages is min range.
Ver 1.6
144
2008-05
ST7713
11.2 Power Booster Circuit
11.2.1 VCI1 generate frome VDD regulator
Source Output Circuit Block REGP AVDD_I Reference Voltage generator Gray reference Circuit Block (Gamma) AVDD_I S1 | S396
VDD CVDD
REGP VC [2:0}
Vci1
REGP AGND Vci1 CVci1 AGND VDD C11 AVDD_I VRH [4:0}
GVDD CGVDD
C12
Charge Pump 1 (VDD * 2)
REGP VMH [6:0}
VCOMH CVCOMH
AVDD CAVDD AGND Vci1 C22 VGH CVGH VCOML Vci1 C23 VGL CVGL Charge Pump 2 (Vci1 * -3,-4,-5) VCL_I REGP VMA [5:0} CVCOML VCOM
Charge Pump 2 (Vci1 * 4,5,6)
Vci1
VGH_I VDD C21 VCL CVCL Charge Pump 4 (VDD * -1) Reference Voltage generator VGL_I
Gate Driver
G1 | G162
VDDI CVDDI
VGL_I
VGH_I
VCL_I
AVDD_I CVREF (Option)
VREF CVCC
VCC
Fig. 11.2.1 Power Booster Structure (1)
Ver 1.6
145
2008-05
ST7713
11.2.2 EXTERNAL COMPONENTS CONNECTION
Pad Name
VDDI VDD VCC AGND DGND C23P, C23N C22P, C22N C21P, C21N C12P, C12N C11P, C11N AVDD VCI1 VGH VGL VCL VREF GVDD VCOMH VCOML VGL
Connection
VDDI (Logic Power) VDD (Analog Power) Connect to Capacitor (Max 3V): VCC -------||-------- GND Analog ground (Connect to GND) Digital ground (Connect to GND) Connect to Capacitor: C23P -------||--------C23N Connect to Capacitor: C22P -------||--------C22N Connect to Capacitor: C21P -------||--- -----C21N Connect to Capacitor: C12P -------||--------C12N Connect to Capacitor: C11P -------||--------C11N Connect to Capacitor: AVDD -------||-------- GND Connect to Capacitor: AVDD -------||-------- GND Connect to Capacitor: VGH -------||-------- GND Connect to Capacitor: VGL -------||-------- GND Connect to Capacitor: VCL -------||-------- GND Connect to Capacitor: VREF -------||-------- GND Connect to Capacitor: GVDD -------||-------- GND Connect to Capacitor: VCOMH-------||--------- GND Connect to Capacitor: VCOML -------||-------- GND Connect to Schottky diode: VGL ------.|------- GND
Rated (Min) Voltage
10.0V 10.0V 10.0V
Typical capacitance value
1.0 uF 1.0 uF 1.0 uF
25.0V; 16.0V* 25.0V; 16.0V* 10.0V 10.0V 10.0V 10.0V 10.0V 25.0V; 16.0V* 25.0V; 16.0V* 10.0V 10.0V 10.0V 10.0V 10.0V 30V
1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF Schottky diode
Note: For the typical specification of capacitor, the surge voltage is 125% of rated voltage. The capacitor of rated voltage of 16V can be only used for the case of VGH < 12.8V and VGL > -12.8V to prevent from stability issue. For normal usage, please use the capacitor of 25V rating.
Ver 1.6
146
2008-05
ST7713
12. Gamma structure 12.1 STRUCTURE OF GRAYSCALE AMPLIFIER
The structure of grayscale amplifier is shown as below. 13 voltage levels (VIP(N)0-VIP(N)12) between GVDD and VGS are determined by the high/ mid/ low level adjustment registers. Positive Frame Negative Frame
GVDD
GVDD
RH
RFP0[3:0]
0 ~3 0R
30R
VRH0: 2R for each step
V0
RFN0[3:0]
0R 0~3
VRH0: 2R for each step
V63
RFP1[4:0]
24R 0~1
VRH1: 4R for each step
V1
RFN1[4:0]
24R 0~1
VRH1: 4R for each step
V62 PKN8[3:0] V60 V57 V52 V43 V31 V20 V11 V6 V3 41 Bits
PKP0[4:0] PKP1[4:0] PKP2[4:0] PKP3[4:0]
V3 V6 V11
PKN7[3:0]
V20
PKN6[3:0]
184R
PKP4[4:0] PKP5[3:0] PKP6[3:0] PKP7[3:0] PKP8[3:0]
V31 V43 V52 V57 V60
41 Bits
PKN5[3:0]
184R
PKN4[4:0] PKN3[4:0] PKN2[4:0] PKN1[4:0] PKN0[4:0]
V62
24R 0~1
V1
OSP1[4:0]
VRL1: 4R for each step
V63
OSN1[4:0]
0~1 24R
VRL1: 4R for each step
OSP0[3:0]
0R 0 ~3
V0
VRL0: 2R for each step
OSN0[3:0]
0R 0~3
VRL0: 2R for each step
RL
30R
Ver 1.6
147
2008-05
ST7713
12.2 Gamma voltage formular (Positive/Negative polarity)
Gray Level 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Voltage Formula (Positive) VINP0 VINP1 V1-(V1-V3)*(16/30) VINP2 V3-(V3-V6)*(11/30) V3-(V3-V6)*(21/30) VINP3 V6-(V6-V11)*(7/30) V6-(V6-V11)*(14/30) V6-(V6-V11)*(20/30) V6-(V6-V11)*(25/30) VINP4 V11-(V11-V20)*(4/30) V11-(V11-V20)*(8/30) V11-(V11-V20)*(12/30) V11-(V11-V20)*(16/30) V11-(V11-V20)*(19/30) V11-(V11-V20)*(22/30) V11-(V11-V20)*(25/30) V11-(V11-V20)*(28/30) VINP5 V20-(V20-V31)*(3/30) V20-(V20-V31)* (6/30) V20-(V20-V31)* (9/30) V20-(V20-V31)* (12/30) V20-(V20-V31)* (15/30) V20-(V20-V31)* (18/30) V20-(V20-V31)* (21/30) V20-(V20-V31)* (23/30) V20-(V20-V31)* (25/30) V20-(V20-V31)* (27/30) VINP6 V31-(V31-V43)*(3/36) V31-(V31-V43)*(6/36) V31-(V31-V43)*(9/36) V31-(V31-V43)*(12/36) V31-(V31-V43)*(15/36) V31-(V31-V43)*(18/36) V31-(V31-V43)*(21/36) V31-(V31-V43)*(24/36) Voltage Formula (Negative) VINN0 VINN1 V1-(V1-V3)*(18/30) VINP(N)2 V3-(V3-V6)*(12/30) V3-(V3-V6)*(22/30) VINN3 V6-(V6-V11)*(7/30) V6-(V6-V11)*(13/30) V6-(V6-V11)*(19/30) V6-(V6-V11)*(25/30) VINN4 V11-(V11-V20)*(4/36) V11-(V11-V20)*(8/36) V11-(V11-V20)*(12/36) V11-(V11-V20)*(16/36) V11-(V11-V20)*(20/36) V11-(V11-V20)*(24/36) V11-(V11-V20)*(28/36) V11-(V11-V20)*(32/36) VINN5 V20-(V20-V32)*(3/36) V20-(V20-V32)*(6/36) V20-(V20-V32)*(9/36) V20-(V20-V32)*(12/36) V20-(V20-V32)*(15/36) V20-(V20-V32)*(18/36) V20-(V20-V32)*(21/36) V20-(V20-V32)*(24/36) V20-(V20-V32)*(27/36) V20-(V20-V32)*(30/36) V20-(V20-V32)*(33/36) VINN6 V32-(V32-V43)*(3/30) V32-(V32-V43)*(5/30) V32-(V32-V43)*(7/30) V32-(V32-V43)*(9/30) V32-(V32-V43)*(12/30) V32-(V32-V43)*(15/30) V32-(V32-V43)*(18/30)
Ver 1.6
148
2008-05
ST7713
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 V31-(V31-V43)*(27/36) V31-(V31-V43)*(30/36) V31-(V31-V43)*(33/36) VINP7 V43-(V43-V52)*(4/36) V43-(V43-V52)*(8/36) V43-(V43-V52)*(12/36) V43-(V43-V52)*(16/36) V43-(V43-V52)*(20/36) V43-(V43-V52)*(24/36) V43-(V43-V52)*(28/36) V43-(V43-V52)*(32/36) VINP8 V52-(V52-V57)*(5/30) V52-(V52-V57)*(11/30) V52-(V52-V57)*(17/30) V52-(V52-V57)*(23/30) VINP9 V57-(V57-V60)*(8/30) V57-(V57-V60)*(18/30) VINP10 V60-(V60-V62)*(12/30) VINP11 VINP12 V32-(V32-V43)*(21/30) V32-(V32-V43)*(24/30) V32-(V32-V43)*(27/30) VINN7 V43-(V43-V52)*(2/30) V43-(V43-V52)*(5/30) V43-(V43-V52)*(8/30) V43-(V43-V52)*(11/30) V43-(V43-V52)*(14/30) V43-(V43-V52)*(18/30) V43-(V43-V52)*(22/30) V43-(V43-V52)*(26/30) VINN8 V52-(V52-V57)*(5/30) V52-(V52-V57)*(10/30) V52-(V52-V57)*(16/30) V52-(V52-V57)*(23/30) VINN9 V57-(V57-V60)*(9/30) V57-(V57-V60)*(19/30) VINN10 V60-(V60-V62)*(14/30) VINN11 VINN12
Ver 1.6
149
2008-05
ST7713
13. Example Connection with Panel direction and Different Resolution
13.1 Application of connection with panel direction Case 1: (This is default case) - 1st Pixel is at Left Top of the panel - RGB filter order = RGB
1st pixel
IC (Bump down) LCD Front side
CF Glass
TFT Glass
Case 2: - 1st Pixel is at Left Top of the panel - RGB filter order = BGR
1st pixel
IC (Bump down) LCD Front side
CF Glass
TFT Glass
Ver 1.6
150
2008-05
ST7713
Case 3: - 1st Pixel is at Righ Bottom of the panel - RGB filter order = RGB
IC (Bump down) LCD Front side
1st pixel
CF Glass
TFT Glass
Case 4: - 1st Pixel is at Righ Bottom of the panel - RGB filter order = BGR
IC (Bump down) LCD Front side
1st pixel
CF Glass
TFT Glass
Ver 1.6
151
2008-05
ST7713
13.2 Application of connection with 132RGBx132 resolution (GM1, GM0 = "10") RAM size=132x132x18-bit Display size = 132RGB x 132 1). Example for SMX=SMY='0'
(0, 0)
1st pixel
2). Example for SMX=SMY='1'
(0, 0)
1st pixel
Ver 1.6
152
2008-05
ST7713
13.3 MicroProcessor Interface applications 13.3.1 8080-Seriers MCU + SPI Interface (RCM = `0x', P68='0', IM2='1') 13.3.1.1 8080-Series MCU Interface for 8-bit data bus (IM1, IM0="00")
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 "0" "0" Note: RCM = `0x' IM2='0', SPI I/F IM2='1', MCU I/F "0" "00" IM2 D/CX WRX RDX D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 13.3.1.1 8080-Series MCU Interface for 8-bit data bus ST7713
13.3.1.2 8080-Series MCU Interface for 16-bit data bus (IM1, IM0="01")
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 D15 to D8 "0" Note: RCM = `0x' IM2='0', SPI I/F IM2='1', MCU I/F "0" "01" IM2 D/CX WRX RDX D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 13.3.1.2 8080-Series MCU Interface for 16-bit data bus ST7713
Ver 1.6
153
2008-05
ST7713
13.3.1.3 8080-Series MCU Interface for 9-bit data bus (IM1, IM0="10")
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D8 to D1 D0 "0" "0" Note: RCM = `0x' IM2='0', SPI I/F IM2='1', MCU I/F "0" "10" IM2 D/CX WRX RDX D8 to D1 D0 D15 to D9 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 13.3.1.3 8080-Series MCU Interface for 9-bit data bus ST7713
13.3.1.4 8080-Series MCU Interface for 18-bit data bus (IM1, IM0="11")
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 D17 to D8 D/CX WRX RDX D7 to D1 D0 D17 to D8 ST7713
Note: RCM = `0x' IM2='0', SPI I/F IM2='1', MCU I/F
"0" "11" IM2
P68 IM1,IM0 IM2 VS, HS, DE PLCK
DGND Fig. 13.3.1.4 8080-Series MCU Interface for 18-bit data bus
Ver 1.6
154
2008-05
ST7713
13.3.2 6800-Seriers MCU + SPI Interface (RCM = `0x', P68='1', IM2='1') 13.3.2.1 6800-Series MCU Interface for 8-bit data bus (IM1, IM0="00")
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 "0" "0" Note: RCM = `0x' IM2='0', SPI I/F IM2='1', MCU I/F "1" "00" IM2 D/CX R/WX E D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 13.3.2.1 6800-Series MCU Interface for 8-bit data bus ST7713
13.3.2.2 6800-Series MCU Interface for 16-bit data bus (IM1, IM0="01")
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D7 to D1 D0 D15 to D8 "0" Note: RCM = `0x' IM2='0', SPI I/F IM2='1', MCU I/F "1" "01" IM2 D/CX R/WX E D7 to D1 D0 D15 to D8 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 13.3.2.2 6800-Series MCU Interface for 16-bit data bus ST7713
Ver 1.6
155
2008-05
ST7713
13.3.2.3 6800-Series MCU Interface for 9-bit data bus (IM1, IM0="10")
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX) RDX(E) D8 to D1 D0 "0" "0" Note: RCM = `0x' IM2='0', SPI I/F IM2='1', MCU I/F "1" "10" IM2 D/CX R/WX E D8 to D1 D0 D15 to D9 D17 to D16 P68 IM1,IM0 IM2 VS, HS, DE PLCK DGND Fig. 13.3.2.3 6800-Series MCU Interface for 9-bit data bus ST7713
13.3.2.4 6800-Series MCU Interface for 18-bit data bus (IM1, IM0="11")
Host RESX TE RESX TE SCL SDA D/CX(SCL) WRX(R/WX ) RDX(E) D7 to D1 D0 D17 to D8 D/CX R/WX E D7 to D1 D0 D17 to D8 ST7713
Note: RCM = `0x' IM2='0', SPI I/F IM2='1', MCU I/F
"1" "11" IM2
P68 IM1,IM0 IM2 VS, HS, DE PLCK
DGND Fig. 13.3.2.4 6800-Series MCU Interface for 18-bit data bus
Ver 1.6
156
2008-05
ST7713
13.3.3 RGB Interface (RCM = `1') 13.3.3.1 RGBInterface for 6-bit Data Width
Host RESX TE CSX D/CX(SCL) SDA VS HS DE PCLK D7 to D2 "0" "0" Note: RCM = `1x' 3Ah="E0h" RESX TE CSX SCL SDA VS HS DE PLCK D7 to D2 D17 to D8 D1 to D0 ST7713
P68, IM2 IM1,IM0 WRX(R/WX) RDX(E) DGND Fig. 13.3.3.1 RGB Interface for 6-bit data width
13.3.3.2 RGBInterface for 16-bit Data Width
Host RESX TE CSX D/CX(SCL) SDA VS HS DE PCLK D5 to D1 D11 to D6 D17 to D13 "0" Note: RCM = `1x' 3Ah="50h" RESX TE CSX SCL SDA VS HS DE PLCK D5 to D1 D11 to D6 D17 to D13 D0, D12 P68, IM2 IM1,IM0 WRX(R/WX) RDX(E) DGND Fig. 13.3.3.2 RGB Interface for 16-bit data width ST7713
Ver 1.6
157
2008-05
ST7713
13.3.3.3 RGBInterface for 18-bit Data Width
Host RESX TE CSX D/CX(SCL) SDA VS HS DE PCLK D5 to D0 D11 to D6 D17 to D12 Note: RCM = `1x' 3Ah="60h" RESX TE CSX SCL SDA VS HS DE PLCK D5 to D0 D11 to D6 D17 to D12 ST7713
P68, IM2 IM1,IM0 WRX(R/WX) RDX(E) DGND Fig. 13.3.3.3 RGB Interface for 18-bit data width
Ver 1.6
158
2008-05
ST7713
14. Revision History
ST7713 Specification Revision History
Version 0.x 1.0 2007/05 Date Preliminary version First issue Modify timing of 3-SPI and 4-SPI. (8.3, p-24; 8.4, p-25) Modify display off function. (10.1.18, p-114) Add notes of 262K read function (10.1.23, p-119; 10.1.33, p-128) Modify cap. rating voltage (11.2.2, p-147) Removed command 2Dh (10.1.24 p-100, p-119) Modify timing of CSX hold time for all I/F(8.1, p-21 8.2,p-23 8.4,p-24) Modify the power system diagram(11.2.1 p-146) Correct the typo of component table(11.2.2 p-147) Revise the waiting time of HW reset(9.18.3 P87) Revise the description of command 01h, 10h,11h, 28h(10.1.2 P105; 10.1.11 P110; 10.1.12 P111; 10.1.18 P114) Modify the description of power on/off sequence(9.15 P82) Remove table 9.18.3.1 reset input timing(9.18.3 P86) Modify the figure of reset timing (9.18.3 P86)
Modify the waiting time of SWReset to 120ms(10.1.2 P104) Modify the waiting time of SLPout mode to 120ms(10.1.12 P110)
Description
1.1
2007/06
1.2 1.3
2007/07 2007/08
1.4
2007/09
1.5
2007/10
1.5.1
2007/11
1.5.2
2007/12
Modify pad arrangement sketch (3 P3) Modify SHUT description (6.3 P16) Modify TESEL description (6.3 P17) Modify RGB Mode2 power on sequence on figure 9.9.15 and table 9.9.6.4 (9.9.6.4 P64) Modify supported MCU interface to 6-bits, 16-bits, 18-bits RGB interface with graphic controller (2 P1) Modify the Figure of RGB Interface for 6-bit data width(fig.13.3.3.1 P156) Modify the Figure of RGB Interface for 16-bit data width(fig.13.3.3.2 P156) Modify the Figure of RGB Interface for 18-bit data width(fig. 13.3.3.3 P157) Add structure of gamma resistance (P147)
1.6
2008/05
Ver 1.6
159
2008-05

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